Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-08-26
2001-09-18
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S038000, C710S120000, C712S001000, C712S200000, C712S204000, C712S205000, C712S206000, C712S208000, C712S209000, C712S210000, C712S215000
Reexamination Certificate
active
06292845
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processing unit for executing instructions of different length. Modern processors are capable of processing instructions of different length. For example, a first or least significant byte of an instruction stream defines an operational code and therefore how many bytes of this particular instruction follow the first byte. These following bytes often define the respective operands of the specific operational code. In some embodiments of modern microprocessors the first byte does not define the length of an instruction but one of the following operands defines the final size of the instruction. Thus, an instruction can have any size within multiples of a byte. Nevertheless, the instruction fetch and decode units need to interpret the respective instruction to evaluate the size of the individual instructions to fetch the remaining parts of the respective instruction. This needs a lot of decoding logic and might slow down a respective processor in particular if an instruction is very long.
Therefore, some reduced instruction set computers only provide instructions with a single format. Hence, in particular 32 Bit or higher microprocessors need a lot of memory to store programs. Especially portable devices and small devices or low cost devices suffer under this requirement.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a data processing unit with a high speed mechanism for fetching and decoding instructions of different length.
Another object of the present invention is to provide means to use short instructions for complex execution tasks.
According to the present invention an instruction fetching unit for loading instructions from a memory processed by a data processing device, whereby said instruction code can be of at least two different lengths, and whereby each instruction contains at least a single bit indicating said instruction sizes, comprises an instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction.
To minimize the instruction size an instruction can use one or more implicit registers. Thus, even so a user cannot freely choose one register from a register file, complex instructions can be executed while minimizing instruction sizes and therefore the size of the instruction memory.
A method of processing instructions in a data processing unit having a pipeline structure, whereby said instruction code can be of at least two different lengths, according to the present invention comprises the steps of:
a) fetching a sequential data stream from an instruction memory containing multiple instructions starting at an instruction address,
b) determining upon at least a single bit of the first data of said data stream said instruction length,
c) issuing said instruction with said length to a decode stage,
d) incrementing said instruction address depending on the instruction length,
e) repeating steps a) through d).
Another method of processing instructions in a data processing unit having at least two pipeline structures, whereby said instruction code can be of at least two different lengths, and whereby each pipeline executes instructions of a respective category, comprises the steps of:
a) fetching a sequential data stream from an instruction memory containing multiple instructions starting at an instruction address,
b) determining upon at least a single bit of the first data said instruction length,
c) determining upon at least a further single bit of said first data said instruction category,
d) determining upon at least a single bit of a second data the instruction length of a subsequent instruction,
e) determining upon at least a further single bit of said second data the instruction category of said second instruction,
f) issuing upon said determinations one or more instructions to the respective pipeline structures,
g) incrementing said instruction address depending on the number of instructions and upon the instruction lengths and types,
h) repeating steps a) through g).
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Arnold Roger D.
Fleck Rod G.
Holmer Bruce
Møller Ole H.
Singh Balraj
Fish & Richardson P.C.
Infineon Technologies North America Corp.
Lee Thomas
Nguyen Tanh
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