Semiconductor device

Details Semiconductor device Semiconductor device

1998-09-30

2001-01-23

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S908000, C257S909000, C257S391000

Reexamination Certificate

active

06177693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having a semiconductor memory formed by locating, in a pattern of diffused layers constituting a memory cell array, a dummy pattern positioned in a region having a low pattern density of diffused layers.
2. Description of Related Art
In general, in most semiconductor devices having a prior art semiconductor memory, a memory cell array constituting the semiconductor memory is formed by repeatedly locating a pattern having the same shape or the same size. For example, a plan view of a flat type mask ROM is shown in FIG.
3
. In a memory cell section
11
and a memory cell section
13
within a memory cell array shown in
FIG. 3
, N
+
diffused layers
14
and gate electrode conductors
15
are repeatedly located with the same line width and with an equal spacing. On the other hand, in a selector section
12
, the N
+
diffused layers
14
and the gate electrode conductors
15
are not located with the equal spacing realized in the memory cell sections
11
and
13
.
Because of this, in the semiconductor device formed to have the prior art semiconductor memory, it was an ordinary practice that the pattern density in the selector section
12
of the memory cell array is lower than that in the memory cell sections
11
and
13
, as shown in the prior art example of FIG.
3
. In the case of forming the pattern of the memory cell array mentioned above, for example, when the N
+
diffused layers
14
is formed, a resist is light-exposed in matching with the shape of the N
+
diffused layers
14
, and thereafter, a developing treatment is carried out to the exposed portion of the resist for patterning the resist, and furthermore, desired N
+
diffused layers
14
are formed using as a mask the resist pattern thus obtained.
Incidentally, in
FIG. 3
, contacts and aluminum interconnections which should be depicted naturally, are omitted, since those do not have a direct relation to the content of the present invention. Furthermore, memory cell transistors and selector transistors formed of the N
+
diffused layers are omitted. However, with these omission, generality of the description of this prior art as the background of the invention is never lost.
In the semiconductor device formed as the prior art semiconductor memory mentioned above, since the N
+
diffused layers
14
and the gate electrode conductors
15
are not located with an equal spacing in the selector section
12
of the memory cell array, a location relation such as a repeated layout pattern is not adopted. Accordingly, the selector section is ordinarily formed to have the pattern density lower than that of the memory cell sections
11
and
13
.
FIG. 4
is a partial enlarged view for illustrating a portion extracted from the memory cell section
11
and the selector section
12
shown in FIG.
3
. Because of a low pattern density of the selector section
12
as mentioned above, an occupying area of a remaining resist region in which no N
+
diffused layer
14
is to be formed, becomes relatively large, so that at the time of patterning the resist, the remaining resist region relatively greatly contracts in proportion to its area because of a heating in the developing treatment. As a result, as shown in
FIG. 4
, there are generated resist-removed patterns
17
a,
17
b
and
17
c
which are larger in shape than an originally designed pattern of N
+
diffused layer
14
.
Here, in the shown prior art example, it is assumed that, in the originally designed pattern, MOS transistors (
1
) are formed by using the N
+
diffused layers
14
at opposite sides of each of specific places A, C and E in
FIG. 4
as a source or a drain, and by using the corresponding gate electrode conductor
15
. Furthermore, MOS transistors (
2
) having the same characteristics as that of the MOS transistors (
1
) are formed by using the N
+
diffused layers
14
at opposite sides of each of specific places B, D and F as a source or a drain, and by using the corresponding gate electrode conductor
15
. However, as mentioned above, because of a low pattern density, the resist-removed patterns
17
a,
17
b
and
17
c
are formed at the position of the corresponding N
+
diffused layers
14
. Namely, the resist-removed patterns different from the originally designed pattern are formed. This means that although the MOS transistors formed at the specific places A, C and E should, in design, have the same characteristics as those of the MOS transistors formed at the specific places B, D and F, because the resist-removed pattern
17
a
becomes enlarged, the MOS transistors are actually formed to have different characteristics, and therefore, are deviated from the original design conception.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device having a semiconductor memory, which has overcome the above mentioned defect.
Another object of the present invention is to provide a semiconductor device having a semiconductor memory, capable of making it possible to form all N
+
diffused layers in the memory cell array as an original designed pattern, thereby homogenizing the characteristics of transistors formed in a memory cell section and in a selector section.
In order to achieve the above mentioned objects, a semiconductor device in accordance with the present invention comprising as a semiconductor memory a memory cell array constituted by continuously locating a plurality of unitary memory cell arrays each including as a basic constituent an arbitrary number of basic patterns formed by ion implantation, the memory cell array being constituted by locating and forming a dummy pattern of the basic pattern in a specific region at least having no memory function existing between the unitary memory cell arrays within an occupying zone of the memory cell array.
In addition, the basic patterns can be formed as an N
+
diffused layer, and the dummy pattern can be formed as a dummy N
+
diffused layer of the N
+
diffused layer. The specific region can be formed as a selector function section existing between the unitary memory cell arrays. Furthermore, in the unitary memory cell arrays and the specific region, gate electrode conductors are located perpendicular to the basic patterns. In a region of the unitary memory cell arrays, the basic patterns can have the same width and can be located with an equal spacing. In addition, in the region of the unitary memory cell arrays, the gate electrode conductors can have the same width and can be located with an equal spacing.


REFERENCES:
patent: 5066997 (1991-11-01), Sakurai et al.
patent: 5416350 (1995-05-01), Watanabe
patent: 62-57222 (1987-03-01), None
patent: 8-28467 (1996-03-01), None

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