Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-13
2001-03-06
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S717000, C438S725000, C438S735000, C438S736000
Reexamination Certificate
active
06197687
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor device having accurate and uniform polysilicon gates and underlying gate oxides. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity reliable interconnect structures.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration require design rules of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. As device scaling plunges into the deep sub-micron ranges, it becomes increasingly difficult to maintain performance and reliability.
Devices built on the semiconductor substrate of a wafer must be isolated. Isolation is important in the manufacture of integrated circuits which contain a plethora of devices in a single chip because improper isolation of transistors causes current leakage which, in turn, causes increased power consumption leading to increased noise between devices.
In the manufacture of conventional complementary metal oxide semiconductor (CMOS) devices, isolation regions, called field dielectric regions, e.g., field oxide regions, are formed in a semiconductor substrate of silicon dioxide by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI).
Photolithography is a conventionally employed to transform complex circuit diagrams into patterns which are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulator, conductor and semiconductor materials. Scaling devices to smaller geometries increases the density of bits/chip and also increases circuit speed. The minimum feature size, i.e., the minimum line-width or line-to-line separation that can be printed on the surface, controls the number of circuits that can be placed on the chip and directly impacts circuit speed. Accordingly, the evolution of integrated circuits is closely related to and limited by photolithographic capabilities.
An optical photolithographic tool includes an ultraviolet (UV) light source, a photomask and an optical system. A wafer is covered with a photosensitive layer, called resist, because of its ability to resist chemicals used in subsequent processing. The mask is flooded with UV light and the mask pattern is imaged onto the resist by the optical system. Photoresists are organic compounds whose solubility changes when exposed to light of a certain wavelength or x-rays. The exposed regions become either more soluble or less soluble in a developer solvent.
There are, however, significant problems attendant upon the use of conventional methodology to form conductive gates with gate oxide layers in between on a semiconductor substrate. For example, when a photoresist is formed on a highly reflective surface, such as polysilicon, and exposed to monochromatic radiation, undesirable standing waves are produced as a result of interference between the reflected wave and the incoming radiation wave. In particular, standing waves are caused when the light waves propagate through a photoresist layer down to the polysilicon layer, where they are reflected back up through the photoresist.
These standing waves cause the light intensity to vary periodically in a direction normal to the photoresist, thereby creating variations in the development rate along the edges of the resist and degrading image resolution. These irregular reflections make it difficult to control critical dimensions (CDs) such as linewidth and spacing of the photoresist and have a corresponding negative impact on the CD control of the shallow isolation trenches.
There are further disadvantages attendant upon the use of conventional methodologies. For example, distortions in the photoresist are further created during passage of reflected light through the highly reflective polysilicon layer which is typically used as a hardmask for etching. Specifically, normal fluctuations in the thickness of the polysilicon layer cause a wide range of varying reflectivity characteristics across the polysilicon layer, further adversely affecting the ability to maintain tight CD control of the photoresist pattern and the resulting shallow isolation trenches.
Highly reflective substrates accentuate the standing wave effects, and thus one approach to addressing the problems associated with the high reflectivity of the polysilicon layer has been to attempt to suppress such effects through the use of dyes and anti-reflective coatings below the photoresist layer. For example, an anti-reflective coating (ARC), such as a polymer film, has been formed directly on the polysilicon layer. The ARC serves to absorb most of the radiation that penetrates the photoresist thereby reducing the negative effects stemming from the underlying reflective materials during photoresist patterning. Unfortunately, use of an ARC adds significant drawbacks with respect to process complexity. To utilize an organic or inorganic ARC, the process of manufacturing the semiconductor chip must include a process step for depositing the ARC material, and also a step for prebaking the ARC before spinning the photoresist.
MOS transistors are used extensively in semiconductor integrated circuit devices. A typical MOS structure is shown in FIG.
1
. The typical MOS structure
100
is formed on a semiconductor substrate
102
. A source
106
region and a drain
108
region are formed in the semiconductor substrate
102
. A gate oxide region
110
is formed on the semiconductor substrate
102
. A polysilicon gate
112
is formed on the polysilicon gate
112
and oxide spacers
114
and
116
are formed on each side of the polysilicon gate
112
. The gate length is represented by the distance
118
and is dependent upon the dimension
120
of the polysilicon gate
112
. Because the strategic approach to improving the speed performance of MOS devices is to continuously reduce device dimensions, especially the gate lengths, it is necessary to decrease the polysilicon dimension
120
. The evolution of MOS device technology has been governed mainly by device scaling and the feature size of the MOS gate length has been scaled down in the effort to increase the speed and scale of integration.
The problem with the further scaling of the MOS transistor gate length is the limitation of photolithography technology. The smallest feature size that photolithography technology can pattern is limited by optical diffraction. Current manufacturing lithography technology that uses UV or deep UV light as the light source is unable to pattern the polysilicon gate to achieve desired reductions in gate length.
One method that has been used to achieve dimensions below the limitations of the photolithography technology is a technique called over etching. However, it is very difficult to control the shape and the size of the structures when using the technique of over etching.
Therefore, what is needed is a method of manufacturing MOS transistors that achieves device dimensions below the limitations of photolithography.
There exists a need for a cost effective, simplified processes enabling the formation of devices which overcome the drawbacks associated with the limitations of conventional photolithography. The present invention addresses and solves the problems attendant upon conventional multi-step, time-consuming and complicated processes for manufacturing semiconductor devices utilizing conventional photolithography.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an efficient cost-effective method of manufacturing a semiconductor device with accurately formed, and reduced gate lengths.
Additional advantages of the present invention will be set forth in the description which follows, and in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out
Advanced Micro Devices , Inc.
Chaudhuri Olik
Pham Hoai
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