Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-18
2001-09-11
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000
Reexamination Certificate
active
06288425
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application is related to Japanese Patent Application No. HEI 9(1997)-241482 filed on Sep. 5, 1997 whose priority is claimed under 35 USC §119, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a SOI.MOSFET (Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor) and a fabrication process therefor. More particularly, the present invention relates to a SOI.MOSFET having a region embedded within a channel region and separated from source/drain regions, and a fabrication process therefor.
2. Description of the Related Arts
MOSFETs fabricated on a SOI substrates such as SOS (Silicon On Sapphire), SIMOX (Silicon Separation by ion implantation of Oxygen) and BSOI (Bonded SOI), offer advantages in low-voltage and high-speed operation. Additionally, SOI.MOSFETs have only three terminals (Gate, Drain and Source), while devices fabricated on a bulk Si require four terminals (Gate, Drain, Source and Substrate). Accordingly, SOI MOSFETs have a comparatively simple construction and result in a smaller layout area as compared with bulk Si devices.
FIGS.
4
(
a
) and
4
(
b
) show a schematic cross section of a conventional MOSFET formed on a bulk Si and its equivalent electrical circuit, also showing a bipolar NPN transistor generated parasitically in this MOSFET structure. In this MOSFET, a gate electrode
23
is formed on a silicon substrate
20
with a gate oxide film
22
interposed therebetween, and source/drain regions
21
are formed in the silicon substrate
20
. Therefore, a base terminal of the parasitic NPN bipolar transistor generated by the source/drain regions
21
and the silicon substrate
20
is tied to the substrate terminal, and the substrate/source junction is reverse biased. As a result, the bipolar NPN transistor has very little effect on the MOSFET operation.
On the other hand, FIGS.
5
(
a
) and
5
(
b
) show a schematic cross section of a conventional SOI.MOSFET and its equivalent electrical circuit, also showing a bipolar NPN transistor generated parasitically in this SOI.MOSFET structure. In this SOI.MOSFET, a silicon oxide film
32
and a top semiconductor layer are successively formed on a silicon substrate
31
; a gate electrode
35
is formed on the top silicon layer with a gate oxide film
34
interposed therebetween; and source/drain regions
33
are formed in the top silicon layer. Therefore, a parasitic bipolar base is floating. In normal operation, holes generated by impact ionization at a drain junction could act as a base current for the parasitic bipolar NPN transistor, creating a positive feedback effect and degrading device electrical characteristics, especially short-channel effect and reduction of a drain/source breakdown voltage. In the case of the SOI.MOSFET with thick top Si channel, it operates in the partially depleted mode, and holes generated by impact ionization flow into a neutral region under the channel, raising a channel potential to increase a drain current, which further increases the number of holes. This leads to a so-called “kink” effect in output characteristics, representing a serious limitation of the SOI.MOSFET.
Possible methods to overcome this limitation are:
a) A use of a SOI.MOSFET constructed on a thicker top Si film and using body contacts to tie a channel region to a fixed potential: this behaves as a bulk Si device suppressing a floating body effect and a parasitic bipolar effect.
However, this method is accompanied by a drawback that the SOI.MOSFET with the channel region tied to the fixed potential by the body contacts consumes area, and the body contact becomes ineffective when the body is fully-depleted.
b) A use of a SOI.MOSFET with a channel region constructed in a low doped thin top Si film in such a way that the channel region is fully depleted. The fully-depleted SOI.MOSFET is theoretically free of the “kink” effect.
However, this method is accompanied by a drawback that, although the “kink” effect is eliminated, it requires the thin top Si film that complicates fabrication processes.
c) A use of a SOI.MOSFET proposed in Japanese Unexamined Patent Publication No. SHO 62(1987)-133762. This device, which is schematically illustrated in
FIG. 6
, has a channel body
40
of N-type and a surface channel
41
of P-type. The “kink” effect is prevented due to recombination of a impact ionization generated holes in the N-type channel body
40
. To prevent leakage current between source/drain regions
42
through the N-type channel body
40
, this must be fully-depleted.
This structure, however, is susceptible to a Short-Channel Effect (SCE) and punch-through, and this SCE will give rise to sub-channel leakage.
e) A use of a SOI.MOSFET described in Japanese Unexamined Patent Publication No. HEI 2(1990)-178965. This device, which is schematically illustrated in
FIG. 7
, has a conductor
50
formed in a channel region and tied to a substrate potential.
This device, however, consumes area and complicates fabrication processes, as in the above case a).
SUMMARY OF THE INVENTION
The present invention provides a SOI.MOSFET comprising: a substrate; a buried oxide film formed on the substrate; a top semiconductor layer formed on the buried oxide film; a gate electrode formed on the top semiconductor layer with a gate oxide film interposed therebetween; source/drain regions of a second conductivity type formed in the top semiconductor layer and on both sides of the gate electrode; and an embedded region of the second conductivity type disposed in the top semiconductor layer and between the source/drain regions and is separated from the source/drain regions and from a top semiconductor/gate oxide interface.
Also, the present invention provides a process of fabricating the above-mentioned SOI.MOSFET, comprising the steps of: (i) forming a buried oxide film and a top semiconductor layer of a second conductivity type successively on a substrate;(ii) implanting impurity ions of a first conductivity type into a surface of the top semiconductor layer thereafter; (iii) forming a gate electrode on the resultant substrate; and (iv) forming a deep channel portion of the first conductivity type underneath the gate electrode by a tilted implantation of impurity ions of the first conductivity type using the gate electrode as a mask to form an embedded region of the second conductivity type, before or after forming source/drain regions separated from the embedded region by implantation of impurity ions of the second conductivity type from above the substrate.
REFERENCES:
patent: 4563805 (1986-01-01), Scovell et al.
patent: 4965213 (1990-10-01), Blake
patent: 5296727 (1994-03-01), Kawai et al.
patent: 5463237 (1995-10-01), Funaki
patent: 5894151 (1999-04-01), Yamazaki et al.
patent: 56-78156 A (1981-06-01), None
patent: 62-133762 A (1987-06-01), None
patent: 2-178965 A (1990-07-01), None
patent: 5-218425 A (1993-08-01), None
patent: 9-293871 A (1997-11-01), None
Nixon & Vanderhye P.C.
Prenty Mark V.
Sharp Kabushiki Kaisha
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