Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-29
2001-05-08
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S206000, C257S207000, C257S210000, C257S211000
Reexamination Certificate
active
06229186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having six-transistor configuration static random access memory (SRAM) calls or other memory cells of a complementary-metal-oxide-semiconductor (CMOS) configuration and a method of producing the same, more particularly relates to a semiconductor memory device which improves the memory cell characteristics by reducing the fluctuation in transistor characteristics due to misalignment of the pattern and by reducing the resistance of the interconnections and which increases the flexibility in layout of interconnections of storage nodes for connection inside the cells and thereby reduces the area of the same and to a method of producing a semiconductor memory device enabling close arrangement of interconnections of storage nodes.
2. Description of the Related Art
An SRAM cell is in general comprised of a flip-flop and two transistors (so-called word transistors) controlled to be conductive or nonconductive in accordance with a supply voltage of a word line and determining whether to connect the two storage nodes of the flip-flop to a bit line. It can be broadly divided into two types according to the difference in the load elements of the flip-flop: a metal-oxide-semiconductor (MOS) transistor load type and a high resistance load type. Of these, the MOS transistor load type has a six-transistor configuration. Depending on the type of the load transistor, a p-type channel NOS transistor (hereinafter referred to as a p-MOS) load type and a thin film transistor (TFT) load type are known.
Looking at a first related art,
FIG. 80
is a plan view of an example of the pattern of the layout of a p-MOS load type SRAM cell according to the related art.
FIG. 80
shows the state after forming the gates of the transistors and omits the illustration of the connections inside the cell and the upper-layer interconnections of the bit lines etc. Instead,
FIG. 80
shows connection of portions connected by the upper-layer interconnections overlappingly on the pattern diagram.
In
FIG. 80
, reference numeral
300
shows the p-MOS load type SRAM cell,
302
a
and
302
b
show p-type active regions in which MOS transistors having n-type channels (hereinafter referred to as n-MOS) are to be formed, and
304
a
and
304
b
show n-type active regions in which p-MOS's are to be formed. The areas surrounding the active regions
302
a
,
302
b
,
304
a
, and
304
b
form element isolation insulating regions using local-oxidation-of-silicon (LOCOS) or trenches.
In this SRAM cell
300
of the related art, the two p-type active regions
302
a
and
302
b
have planar shapes bent outward substantially perpendicularly. At the two sides straddling each of the bent portions are formed a drive transistor Qn
1
(or Qn
2
) and a word transistor Qn
3
(or Qn
4
). A word line serving also as the polycrystalline silicon gate electrodes of the word transistors Qn
3
and Qn
4
is laid intersecting both of the two p-type active regions substantially perpendicularly and running between cells in the horizontal direction in FIG.
80
. As opposed to this, common gate lines
306
a
and
306
b
serving also as polycrystalline silicon gate electrodes of the drive transistors Qn
1
and Qn
2
are formed separately for each cell. That is, the common gate line
306
a
perpendicularly intersects the p-type active region
302
a
in the vertical direction in
FIG. 80
, while the common gate line
306
b
perpendicularly intersects the p-type active region
302
b
in the same direction.
These common gate lines
306
a
and
306
b
perpendicularly intersect the n-type active regions
304
a
and
304
b
, respectively, as wall. Due to this, a p-MOS (load transistor Qp
1
or Qp
2
) is formed at each of the n-type active regions
304
a
and
304
b.
The load transistor Qp
1
and the drive transistor Qn
1
constitute a first inverter, while the load transistor Qp
2
and the drive transistor Qn
2
similarly constitute a second inverter. Note that each common gate line
306
a
and
306
b
has a branch line near the mid portion. As shown by the connections in
FIG. 80
, an input of one inverter is connected to the output of the other inverter by a second-layer polycrystalline silicon layer. Further, a supply line of a power voltage V
cc
, a supply line of a common potential V
ss
, and bit lines BL
1
and BL
2
are connected as shown in the figure.
Looking at a second related art, in recent years, for example, “A LOW COST MICROPROCESSOR COMPATIBLE, 18.4 &mgr;m
2
, 6-T BULK CELL TECHNOLOGY FOR HIGH SPEED SRAMS. VLSI Symposium Report, pp. 65-66, 1993” proposed a split word line type SRAM cell with word lines laid split for each word transistor.
FIG. 81
is plan view of the pattern of the layout of the split word line type cell described in that paper and is shown in the same way as FIG.
80
.
In the split word line type SRAM cell
310
, a p-type active region
312
in which n-MOS transistors are to be formed it formed in common between the inverters and word transistors and is made common between cells adjoining in the word line direction as well. In the same way, an n-type active region
314
in which p-MOS transistors are to be formed is formed in common between inverters and between cells adjoining in the word line direction.
Note that, the connections shown in
FIG. 81
are basically the same as those in
FIG. 80
, but here the serial connections of the p-MOS's and n-MOS's of the inverters are comprised by second-layer polycrystalline silicon layers, the connections between the serial connecting points and the inputs of the other inverters, the supply line of the power voltage V
cc
, etc. are comprised by third-layer polycide layers, and the supply line of a common potential V
ss
and the bit lines are comprised by fourth-layer metal interconnections.
Turning now to the problems to be solved by the invention, in general reduction of the pattern size is indispensable in increasing the degree of integration and the memory capacity of semiconductor memory devices. This reduction of the pattern size is achieved by forming finer patterns, reducing the amount of mismatch in alignment of photo masks between different patterns, and adopting self-alignment technology where mismatch between patterns does not become a problem.
At the present time, the former finer patterns are formed by improving the resist materials, increasing the precision of producing of the interconnections etc. using the resist as a pattern transfer mask, and shortening the wavelength of the light emitted from the exposure system from g-rays to KrF excimer lasers, ArF excimer lasers, and on to X-rays.
On the other side, looking at the latter mismatch between patterns, the amount of mismatch can be tremendously reduced while maintaining high characteristics and reliability by adopting self-alignment technology. In the actual manufacture of devices, however, the types of processes in which self-alignment technology can be applied are limited. In other processes, the amount of mismatch between patterns depends on the mechanical precision of the exposure system. The mechanical precision cannot be improved to a great degree, so the amount of mismatch is not being reduced at the same pace as the miniaturization of the patterns themselves at the present time.
Therefore, it is required to design patterns so that even if mismatch occurs between patterns, it will not become a problem as seen from the characteristics and reliability—particularly in processes where self-alignment technology cannot be adopted.
The SRAM cells of the first and second related arts explained above with reference to
FIGS. 80 and 81
, however, were not designed with sufficient consideration to the mismatch between patterns.
For example, in the SRAM cell
300
of the first related art shown in
FIG. 80
, the p-type active regions
302
a
,
302
b
for forming the n-MOS's are bent outward. Despite the patterns on the mask being patterns of combinations of rectangular shapes, the actually
Fenty Jesse A.
Lee Eddie C.
Sonnenschein Nath & Rosenthal
Sony Corporation
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