Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-31
2001-08-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S455000
Reexamination Certificate
active
06271107
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to methods and structures for processing a semiconductor substrate into a semiconductor device having a polymeric layer.
BACKGROUND OF THE INVENTION
Flip chip bonding processes are very popular for communicating a chip to a circuit substrate such as circuit board. In an exemplary flip chip bonding process, plural solder bumps are formed on the semiconductor chip so that the bumps are on the face of the chip. The bumped chip is then flipped over and is mounted on the circuit substrate so that the bumps contact conductive pads on the circuit substrate. The solder bumps are then heated so that the solder bumps form solder joints coupled to the pads, thus communicating the chip to the circuit substrate.
Flip chip bonded chips have a number of advantages over other chip connection processes such as wire bonding. For example, the circuit substrate in a wire bonded assembly typically has pads in a ring-like pattern, and a chip is secured within the ring-like pattern in a face up position. Fine wires connect the pads on the circuit substrate to pads located at the periphery of the upward facing face of the chip. In assemblies such as these, the number of input/output (I/O) connections between the chip and the substrate are limited and the space occupied by the wires is relatively large.
On the other hand, flip chip bonded chips communicate with an underlying circuit substrate without the use of an intermediate conducting structure such as a bonding wire. Consequently, shorter signal paths exist between the chip and the circuit substrate in a flip chip assembly than in an assembly such as a wire bonded assembly. Moreover, since flip chip bonded chips do not require intermediate conducting structures such as bonding wires to communicate the chip and the circuit substrate, the materials and processing steps used in the electrical assembly are reduced. Reducing the materials and processing steps significantly reduces the cost of the electrical assembly. In addition, in a flip chip assembly, the I/O connections are not limited to the peripheral region of the chip face, as is the case in a typical wire bonded assembly. In a flip chip assembly, I/O connections (e.g., solder joints) may be present across the face of the chip. The increased number of I/O connections between the chip and the circuit substrate in a flip chip assembly provides more signal pathways between the chip and the circuit substrate.
Although flip chip bonding provides a number of advantages, flip chip bonding also presents a number of problems. For example, stenciling can be used to form solder bumps on chips to be flip chip bonded. In a typical stenciling process, a rigid stencil is placed on a semiconductor wafer having a number of chips. The stencil is disposed over the wafer so that the apertures of the stencil are aligned with pads on the individual chips. Solder paste is then deposited through the stencil apertures and onto the pads. The deposited solder is then reflowed to form solder bumps on the wafer. After reflow, the stencil is separated from the wafer. When the mask is separated from the wafer, the stencil may inadvertently contact one or more of the solder bumps dislodging them from the wafer. If this occurs, it may be necessary to rework the wafer to maximize the yield of bumped chips. Reworking wafers is expensive and time consuming. Although conventional photoimageable and strippable solder masks can be used in place of the rigid stencil described above, the use of solder masks requires additional process steps which increases the cost of the formed electrical assembly.
Also, even though a flip chip can advantageously have a large number of solder joints on the face of the chip, the increased number of solder joints creates other problems. For example, lead containing solder can emit alpha particles, which can pass into a chip to which the solder is bonded. The absorbed alpha particles can cause cells in the chip to flip states, thereby causing a memory error in the chip. Errors such as these are known as “soft errors”, and tend to increase as chip features become smaller and as the number of solder joints increase.
Furthermore, solder joints are generally inflexible. During operation, a chip in a chip assembly heats and cools as it is turned on and off. Since the chip and the circuit substrate are typically made of dissimilar materials which have different thermal expansion properties, the chip and the circuit substrate can move with respect to each other. This relative movement deforms the solder joints and places them under mechanical stress. The stress, when repeatedly applied to the joints with repeated operation of the chip, can result in breakage of the solder joints over time. Accordingly, the likelihood of solder joint breakage is more likely in a flip chip assembly than in, e.g., a wire bonded chip assembly, because the number of solder joints on the chip are significantly greater in a flip chip assembly than in a wire bonded chip assembly.
It would be desirable to provide methods and structures which can improve the reliability of an electrical assembly having flip chips, while also reducing the steps and materials used to form an electrical assembly having flip chips.
SUMMARY OF THE INVENTION
One embodiment of the invention relates to a method for processing a semiconductor substrate. The method includes forming a laminate comprising a semiconductor substrate having a conductive region, a polymeric layer, and a release layer, where the polymeric layer is disposed between the semiconductor substrate and the release layer. An aperture is formed in the polymeric layer and the release layer to expose the conductive region, and a solder composition is deposited within the aperture. While in the aperture, the solder composition is reflowed to form a solder bump. After the solder bump is formed, the release layer is separated from the polymeric layer.
Another embodiment of the invention can be directed to a bumped semiconductor substrate. The bumped semiconductor substrate includes a semiconductor substrate having a conductive region, a polymeric layer on the semiconductor substrate; and a release layer on the polymeric layer. The polymeric layer and the release layer have a common aperture disposed over the conductive region, and the common aperture includes a solder bump electrically coupled to the conductive region.
Other embodiments of the invention relate to methods for forming electrical assemblies such as multichip modules and chip scale packages.
These and other embodiments of the invention will become apparent to those skilled in the art from the following detailed description, the accompanying drawings, and the appended claims.
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Jiang Hunt Hang
Massingill Thomas
McCormack Mark Thomas
Coudert Brothers
Fujitsu Limited
Le Dung A
Nelms David
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