Mixed mode device

Details Mixed mode device Mixed mode device

2000-01-28

2001-05-22

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S275000, C257S341000

Reexamination Certificate

active

06236092

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a design of a mixed mode device, and more particularly to a metal pad positioned on the top of the mixed mode device for connecting to a test device.
2. Description of the Related Art
Conventionally, the most commonly test pattern in a high frequency mixed mode device is a metal-oxide semiconductor transistor with a finger-type polysilicon layer as shown in FIG.
1
.
Referring to
FIG. 1
, a well
102
is formed within a provided substrate
100
. A conductive type of the well
102
and a conductive type of the substrate
100
are oppositive. A finger-type polysilicon layer
104
is formed over the substrate
100
and is positioned on the well
102
. The finger-type polysilicon layer
104
is used as gates of MOS transistors. Heavily doped regions are formed within the substrate
100
beside the finger-type polysilicon
104
. Source/drain regions
106
/
108
are thus formed. A finger-type first metal layer
110
is formed over the gates. The first metal layer
110
electrically couples with the drain regions
108
. A second metal layer
112
with a rectangular shape is formed over the first metal layer
110
. The second metal
112
electrically connects to the source regions
106
through vias
114
.
A network analyzer is used to test quality of the mixed mode device. The gates of polysilicon
104
are connected to a transmission side of the network analyzer to transfer a current signal. The drain regions
108
of the MOS transistors are connected to a receiver side of the network analyzer to receive the current signal. The source regions
106
and gates of the MOS transistors are grounded.
Since the second metal layer
112
connects to the source regions
106
, the source regions
106
are grounded through the second metal layer
112
. A circuitry of the mixed mode device is shown in
FIG. 2. A
voltage is applied on the gate
204
of a MOS transistor. A current is brought from the drain region
202
of the MOS transistor. The mixed mode device shown in
FIG. 1
comprises several MOS transistors. Each source region
106
of the MOS transistors is connected to the second metal layer
112
through the vias
114
. Areas of the second metal layer
112
over the source regions
106
are the same. Currents of the source regions
106
are the same so that a concourse of the currents to the second metal layer
112
makes a voltage of the second metal layer
112
become higher and higher. A negative feedback is thus formed at the source side.
SUMMARY OF THE INVENTION
The invention provides a mixed mode device. Area of the second metal layer of the mixed mode is adjusted according to current from source regions. Resistance of the second metal layer is thus decreased to reduce the negative feedback at the source regions.
The provided mixed mode device of the invention comprises a substrate having a well therein, a polysilicon layer over the substrate, a first metal layer over the polysilicon layer, and a second metal layer over the first metal layer. A conductive type of the well and a conductive type of the substrate are oppositive. A part of the polysilicon layer is positioned over the well. Heavily doped regions are further formed in the well beside the polysilicon layer. The polysilicon layer is used as gates of MOS transistors, and the heavily doped regions are used as source/drain regions of the MOS transistors. The first metal layer over the gate has a finger structure which electrically couples with the drain regions of the MOS transistors. The second metal layer electrically couples with the source regions through vias.
The second metal has two portions. One portion comprises rectangles and the other portion comprises trapezoids. The rectangles are over and connecting to the vias. Each of the trapezoids respectively cross over source region-gate-drain region areas. The top border of each trapezoid is shorter than the bottom border so that a rectangle adjacent the top border is smaller than a rectangle adjacent the bottom border. Unit area of the second metal layer is thus increased to reduce resistance of the second metal layer. Accordingly, the negative feedback from increasing current is prevented. Furthermore, the parts of the second metal layer connecting to the vias are rectangular. The vias are completely covered by the second metal layer.


REFERENCES:
patent: 4158807 (1979-06-01), Senturia
patent: 5283452 (1994-02-01), Shih et al.
patent: 5925901 (1999-07-01), Tsutsui
patent: 6020613 (2000-02-01), Udomoto et al.

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