Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-01-13
2001-08-21
Wiley, David A (Department: 2155)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C709S232000
Reexamination Certificate
active
06279052
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to data transfer. More specifically, the invention relates to transfers of data between a host system and a serial bus.
(2) Related Art
The existing systems provide for transmission of data across high speed serial buses. One existing protocol for serial data transmission is defined in IEEE Std. 1394-1995, IEEE Standard for a High Performance Serial Bus published Aug. 30, 1996. Revisions to this standard can be expected from time to time. Two such revisions are 1394a Draft Standard for a High Performance Serial Bus (Supplement) and 1394b Draft Standard for a High Performance Serial Bus (Supplement) (1394a and 1394b respectively). These protocols are generically referred to herein as “1394” protocols. Similarly, systems implementing these protocols are generically “1394” systems. An analogous labeling convention is employed throughout.
In the 1394 protocols as with most serial protocols, the data to be sent is packetized in a host system and a layer of buffering is provided between the memory and any transport layer to store the packets awaiting transfer and/or packets received waiting to be forwarded to the memory of the host system.
FIG. 1
is a block diagram of a prior art system employing a static buffer layer. In this system a processor
1
is coupled via a memory controller
4
to a memory
3
. The memory controller
4
is also coupled to a graphics card
5
. The chipset
2
includes the memory controller
4
, an arbitration unit
6
coupled to the memory controller, and a plurality of direct memory access controllers (DMA)
11
coupled to the arbitration unit
6
. TheS DMA load or empty a plurality of FIFOs which provide buffering for packets received from or to be sent to the serial bus
18
. A link layer
16
provides the interface between the FIFOs and a transceiver
17
. The transceiver
17
couples to serial bus
18
and transmits and receives packets across serial bus
18
.
For outgoing transactions, a driver
10
which executes on processor
1
packetizes the data from memory and transfers the packet into the appropriate transfer FIFO via DMA controllers
11
, in this case FIFO
12
for asynchronous transfers and FIFO
14
for isochronous transfers. This requirement that the packets be created and stored requires a certain buffer size at least equal to the packet size. Thus, employing this prior art technique the options for reducing chipset die size going forward appear quite limited.
FIG. 4
is a diagram of a prior art packet. The packets contain a packet header, a header cyclic redundancy check value (CRC), data, and a data CRC. The packet header and the CRCs contribute a fixed overhead existing regardless of the amount of data packetized.
The 1394 protocols support a four transaction types i) asynchronous transmits, ii) asynchronous receives iii) isochronous transmits and iv) isochronous receives. Each of these transaction types has an associated FIFO of static size in which the size is selected at manufacture based on an optimal packet size for the 1394 protocol implemented. In the case of 1394a, which operates with speeds of up 400 megabits per second, the size of each transaction FIFO is two kilobytes. As speeds increase with subsequent generations of 1394 protocol, the size of the optimal buffers will increase proportionally. Significantly, the buffers represent a large proportion of the die area required to create the chipset. Increases in buffer size will further increase both die size and the proportion of the die area allocated to buffer area. This increase in real estate required is expected to significantly increased cost of the chipsets.
Accordingly, it would be desirable to have a method and apparatus which would employ total buffering smaller than use of optimal packet sized buffers for each transaction type, without loss of functionality. In this way, the area required to create the chipset could be reduced with a corresponding reduction in cost.
BRIEF SUMMARY OF THE INVENTION
An apparatus for conducting serial bus transactions is disclosed. In one embodiment, a transceiver is provided. A plurality of FIFOs are allocatable from a shared buffer pool, each FIFO corresponding to a serial bus transaction type. A plurality of direct memory access controllers (DMAs) are coupled to the FIFOs and fill or empty the FIFOs. A link layer provides an interface between the transceiver and the FIFOs permitting the transceiver to conduct transactions to and from the FIFOs.
In another embodiment of the invention, again a transceiver is provided. A FIFO smaller than a default packet size of an associated transaction type is employed. A link layer provides an interface between the small FIFO and the transceiver. The link layer also sets a control register to dictate packet size so that an upstream system can handle transfers of the packet size eventhough constrained by the small FIFO.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Wiley David A
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