Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-14
2001-09-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000, C257S377000, C257S389000, C257S647000, C257S754000
Reexamination Certificate
active
06291860
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing high-density integrated semiconductor devices exhibiting reliable, adherent, well-aligned contacts to source, drain, and gate electrode regions of active devices such as MOS transistors formed in or on a semiconductor substrate. The invention has particular utility in manufacturing high-density integration semiconductor devices, including multi-level devices, with design rules of 0.18 micron and under.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design rules of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Recently, there has been a demand for large-scale and ultra small-sized static random access memory (SRAM) devices in high performance complementary metal-oxide-semiconductor (CMOS) microprocessors. Manufacture of such devices require process compatibility with known salicide-CMOS technologies in order to avoid increasing the number of process steps. Conventional methods for reducing cell size include forming local interconnects to couple gates and doped regions. However, technologies utilizing an insulator-capped gate electrode are difficult to adapt for use with a salicide (self-aligned silicide) process, because they require the use of several additional photolithographic masks to etch off the insulator cap in the peripheral areas and to separately dope the gate and source/drain regions. While a damascene type local interconnect process affords some simplification of the fabrication scheme, such processing still requires additional chemical vapor deposition (CVD) of dielectric material, etching, chemical-mechanical planarization (CMP), photolithographic, and metallization steps. Another conventional technique for achieving smaller cell size involves shared-contact technology; however, such methods require contact implantation processing undesirably involving one or more masks in order to avoid junction leakage at the region of the contact on the LDD (lightly doped drain) regions.
Thus, there exists a need for a process for forming self-aligned silicide (i.e., salicide) contacts to transistor source and drain regions without reliance upon either a local interconnect or shared-contact. There exists a further need for methodology enabling the formation of contacts of proper size and alignment that reliably land on the desired areas of the semiconductor substrate and do not short to the gate. Moreover, there exists a need for a process for forming electrical contacts to transistor source and drain regions without shorting into the shallow trench isolation (STI) edge, and provide relatively low resistance local routing and ability to remote the contacts. There is also a need for a process which is compatible with conventional process flow for the manufacture of SRAMS and similar devices employing MOS transistors.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a high density integrated semiconductor device with an improved self-aligned contact structure.
Another advantage of the present invention is a method of forming contacts of proper size and alignment that reliably land on desired source and drain regions of a MOS transistor.
Still another advantage of the present invention is a method for forming contacts to source and drain regions of a MOS transistor which do not short into the edges of isolation regions formed in the semiconductor substrate, provide relatively low resistance local routing, and ability to remote the contacts.
A still further advantage of the present invention is a high-density SRAM or similar type semiconductor device comprising MOS transistors with source and drain regions having self-aligned contacts of proper size and reliable alignment.
Additional advantages, and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises:
providing a semiconductor wafer having a surface, the semiconductor wafer comprising:
a pair of spaced apart isolation regions formed therein and extending from the wafer surface to a depth below the surface;
a pair of spaced apart source and drain regions formed in the space between the isolation regions;
a patterned, thin gate insulating layer formed on said wafer surface and comprising a portion (a) between said spaced apart source and drain regions and the respective adjacent edge portions of the source and drain regions; and portions (b) on the edge portions of the source and drain regions, opposite to and spaced apart from portions (a) and extending to the periphery of an adjacent one of the pair of isolation regions;
a gate electrode in overlying contact with portion (a) of the gate insulating layer;
source and drain electrodes, each having side surfaces, a top surface and a bottom surface, and each in overlying contact with a respective portion (b) of the gate insulating layer and extending over and in contact with at least a portion of the adjacent isolation region; and
insulative sidewall spacers formed on the side surfaces of each of the gate, source, and drain electrodes;
depositing a photoresist layer over the exposed surfaces of the wafer;
patterning the photoresist to form a mask exposing portions of the top surface and sidewall spacers of the source and drain electrodes;
selectively removing the exposed portions of the sidewall spacers, thereby exposing portions of the side edge surfaces of the source and drain electrodes;
forming an electrical conductor in ohmic contact with the exposed top and side surfaces of the source and drain electrodes, the conductor extending over and in ohmic contact with at least a portion of the adjacent source or drain region.
According to another aspect of the present invention, a semiconductor device having improved self-aligned contacts to source and drain regions of the device is provided, comprising:
a semiconductor wafer having a surface, said semiconductor wafer comprising:
a pair of spaced apart isolation regions formed in the wafer surface and extending from the surface to a depth below the surface;
a pair of spaced apart source and drain regions formed in the space between the isolation regions;
a patterned thin gate insulating layer formed on the portion of the wafer surface intermediate the source and drain regions and on portions of the wafer surface intermediate the source and drain regions and their respective adjacent isolation regions;
a gate electrode formed over and in contact with the gate insulating layer intermediate the source and drain regions, with insulative sidewall spacers formed on opposite side surfaces thereof;
source and drain electrodes comprising side surfaces, a top surface, and a bottom surface, formed over respective portions of the source and drain regions, over the portions of the gate insulating layer intermediate the source and drain regions and their respectively adjacent isolation regions, and over at least a portion of the adjacent isolation regions;
insulative sidewall spacers formed on opposite side surfaces of each of the source and drain electrodes; and
electrical conductors each in ohmic contact with the top surfaces of respect
Advanced Micro Devices , Inc.
Lee Eddie
Warren Matthew E.
LandOfFree
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