Semiconductor memory device with reduced current consumption in

Details Semiconductor memory device with reduced current consumption in Semiconductor memory device with reduced current consumption in

1998-07-15

1999-05-11

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Data refresh

365226, 36518905, 36518909, G11C7/00

Patent

active

059035072

ABSTRACT:
In a normal operation mode, a dynamic random access memory DRAM has a plurality of memory mats simultaneously selected. During a refresh operation, refreshing is effected simultaneously on a plurality of memory sub-arrays in one of the memory mats. A control signal only for one memory mat is required to be driven, so that a current consumption in a data holding mode can be reduced. Further, by reducing a circuit operation speed, a peak current can be reduced.

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Takashima, D., et al: "A Novel Power-Off Mode for a Battery-Backup DRAM", 1995 Symposium on VLSI Circuits of Technical Papers, pp. 109-110.
Kitsukawa, Goro, et al: "256Mb DRAM Technologies for File Applications", 1993 IEEE International Solid-State Circuits Conference, pp. 48-49.

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