Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-03-05

2001-05-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

Reexamination Certificate

active

06233192

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a synchronous DRAM (dynamic RAM).
2. Description of the Related Art
In recent years, though various memory LSIs have been proposed in order to eliminate an access gap between a microprocessor and a memory, all of the LSIs are characterized in that input and output are performed synchronously with an external clock to increase data transfer rate. There is a memory called synchronous DRAM (hereinafter referred to as ‘SDRAM’) among the synchronous type memories.
The SDRAM is provided with an auto-refresh and a self-refresh as a refresh mode.
FIG. 8
is a timing chart showing an auto-refresh action of a SDRAM chip. At time t5, when a row address strobe signal /RAS and a column address strobe signal /CAS are at low levels and a write enable signal /WE and a clock enable signal CKE are at high levels, the auto-refresh is actuated. At time t6, when signals similar to those at time t5 are inputted, the auto-refresh is repeated again.
In the auto-refresh a refresh address is generated in an internal refresh counter, a row of memory cells corresponding to the refresh address is refreshed, and then the row of memory cells is automatically put in a precharged state. In order to refresh all memory cells it is usually sufficient to repeat the auto-refresh 4096 times.
FIG. 9
is a timing chart showing the self-refresh action of the SDRAM chip. At time t7, after a row address strobe signal /RAS, a column address strobe signal /CAS and a clock enable signal CKE become low and a write enable signal /WE becomes high, the self-refresh is actuated while a clock enable signal CKE is at a low level.
In the self-refresh the action similar to the auto-refresh is automatically performed at constant intervals by an internal timer.
In a refresh system standardized by JEDEC, since it has been determined that a plurality of memory banks are alternately refreshed, the respective memory banks can not be refreshed simultaneously, or concurrently with a refresh action on one of the memory banks, the other of the memory banks can not be accessed. Also, a bank to be refreshed can not be designated from the banks.
As conventional technique for providing a synchronous type DRAM having a plurality of memory banks, each memory of which is accessible independently, with a function for refreshing the plurality of memory banks simultaneously, a function for allowing one or more memory banks of the plurality of memory banks to be designated for refreshing, and a function for performing memory access concurrently with refresh action and independently therewith, thereby improving memory function, there are Japanese Unexamined Patent Publications JP-A 9-139074 (1997), JP-A 7-226077 (1995), JP-A 8-77769 (1996), JP-A 7-169266 (1996), etc.
FIG. 7
shows a block diagram of a configuration example of SDRAM disclosed in Japanese Unexamined Patent Publication JP-A 9-139074 (1997) as one of the conventional techniques.
The SDRAM of the configuration example includes a memory array
200
A configuring a memory bank (BANKA) and a memory array
200
B configuring a memory bank (BANKB). Each of the memory arrays
200
A and
200
B includes dynamic type memory cells arranged in a matrix, each of the memory cells being configured with a capacitor for storing data and a MOS transistor with a gate connected to word lines (not shown) and a drain connected to complementary bit lines (not shown).
One of the word lines (not shown) in the memory array
200
A is driven to a selection level according to the decode result of a row address signal generated by a row decoder
201
A. The not illustrated complementary bit lines in the memory array
200
A are connected to a sense amplifier and column selecting circuit
202
A. The amplifier in the sense amplifier and column selecting circuit
202
A is an amplifying circuit for detecting fine voltage differences appearing in respective complementary bit lines by reading data from the memory cells to amplify the fine voltage differences. The column switching circuit in the sense amplifier and column selecting circuit
202
A is a switching circuit for selecting the complementary bit lines individually to connect the selected complementary bit line to a common bit line
204
. The column switching circuit performs a selecting action according to a decode result of a column address signal generated by a column decoder
203
A.
On the memory array
200
B side, similarly, a row decoder
201
B, a sense amplifier and column selecting circuit
202
B and a column decoder
203
B are provided.
The complementary common bit line
204
is connected to an output terminal of an input buffer
210
and an input terminal of an output buffer
211
. An input terminal of the input buffer
210
and an output terminal of the output buffer
211
are connected to 8 bit data input/output terminals I/O 0 to I/O 7.
Row address signals and column address signals supplied from the address input terminals A
0
to A
11
are taken in a column address buffer
205
and a row address buffer
206
in address multiplex forms. The address signals supplied are held in the respective buffers. The row address buffer
206
takes in a refresh address signal output from a refresh counter
208
as a row address signal in a refresh action mode. Output of the column address buffer
205
is supplied as preset data for a column address counter
207
, and the column address counter
207
outputs column address signals serving as the preset data or values produced by sequentially incrementing the output column address signals towards the column decoders
203
A,
203
B in accordance with an action mode specified by a command.
A control circuit
212
, which is not limited, is one of a type to which external control signals such as clock signal CLK, clock enable signal CKE, chip selecting signal /CS, column address strobe signal /CAS, row address strobe signal /RAS, write enable signal /WE, data input/output mask control signal DQM (not shown), etc. and control data from the address input terminals A
0
to A
11
are supplied to produce internal timing signals for controlling action mode of the SDRAM and action of the circuit block based upon variations of levels, etc. of these signals. For this reason, the control circuit
212
is provided with a control logic (not shown) and a mode register
30
. It is to be noted that the symbol ‘/’ represents a low enable signal.
The clock signal CLK serves as a master clock for the SDRAM and the other external input signals are latched synchronously with a rising edge of the internal clock signal CLK. The chip selecting signal /CS instructs start of command input cycle by the low level. The respective signals /RAS, /CAS and /WE are signals different in function from corresponding signals of a normal DRAM and used when command cycle is set.
The clock enable signal CKE is a signal for indicating validity of the next clock signal, wherein it is determined that the rising edge of the next clock signal CLK is valid when the signal CKE is at a high level, while it is determined that the rising edge is invalid when the signal CKE is at a low level. Further, in a read mode not shown, an external control signal for controlling output enable on an output buffer
211
is supplied to the control circuit
212
and, when the signal is, for example, at a high level, the output buffer
211
is put in a high impedance state.
The row address signal is defined by levels of the address input terminals A
01
to A
10
in bank active command cycle synchronized with the rising edge of the clock signal CLK (internal clock signal). An input from the address input terminal A
11
is regarded as a bank selecting signal in the bank active command cycle. That is, when the input of the terminal A
11
is at a low level, the memory bank BANKA is selected and when the input is at a high level, the memory bank BANKB is selected. A selection control for the memory bank, which is not limited particularly, can be performed by such a processin

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