Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Utility Patent
1998-05-18
2001-01-02
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S005000, C714S048000
Utility Patent
active
06170039
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory controller. In particular, the present invention relates to a memory controller for interchanging a memory when a memory error occurs in an interleave memory system.
For a memory device of a computer such as a main storage, an interleave system has been heretofore employed in order to allow access at high speed. In the interleave system, an address is exclusively given to a set of a plurality of memories (hereinafter, called a bank) that can be accessed in parallel. In this case, if the object bank is different, a new access can be made in parallel to another bank without waiting for the end of access of the object bank during execution. Particularly, the bank addresses are often given so that different banks may be sequentially used when the addresses to the memory are continuous, utilizing the characteristic that continuous access to the memory is often executed in an ascending or descending sequence.
On the other hand, since memory capacity required for an information processing system is different depending on users' needs or the object to be processed, the memory capacity may be varied in many information processing systems. Therefore, users are capable of selecting adequate memory capacity within the permissible range of the information processing system, and expanding the memory capacity later, depending on the memory requirements. In order to realize such a requirement, a memory device may be composed of a loading unit called a memory module.
A correspondent relationship between the memory module and the bank may be assumed to have any of the following cases: a case in which one memory module forms one bank; a case in which a plurality of banks are included in one memory module; and a case in which one bank is formed of a plurality of memory modules. Moreover, only one type of memory module is sometimes provided, while it is also probable that a larger capacity memory module may be provided because of the change in a generation of memory chip capacity.
If a memory module of different capacity is provided, it is important for protection of hardware resources of users to allow the use of a new large capacity module in combination with an old small capacity module. In order to allow co-existence of memory modules having different capacities, it is required to introduce a method of supplying addresses without any inconsistent problem with various combinations of different memory modules. In one conceivable method, the continuous addresses start from the maximum address before expansion are given to the expanded memory modules. In this case, since the interleave in the added address areas is executed in a closed manner within the expanded memory modules, the expanded memory modules are required to have the sufficient number of banks. However, since the depth in the address direction increases for the bit width with increase of capacity of a memory chip, the memory capacity consequently increases in the memory modules having a plurality of banks. It is thus impossible to provide memory modules of a small expansion unit.
Therefore, the applicant has proposed a technique in which, in order to keep the expansion unit small and to acquire an interleaving factor (a degree of multiplexing or the number of ways), an interleave is variable depending on the structure of memory device and memory module and also the interleave is capable of extending over the expanded modules and those already provided.
On the other hand, in order that an operating system (OS) is normally operated on the main storage, there may be a need to fixedly acquire a constant continuous space which is error free (without error) from a predetermined address (for example, address “0”) of a physical address. In this case, if a memory error is occurred, the problem cannot be solved by deallocating a page alone including an erroneous area (by deallocating the page). The whole memory module including the error is therefore deallocated, and thus performance is considerably deteriorated.
SUMMARY OF THE INVENTION
In order to solve the above problems, it is an object of the present invention to provide a method of avoiding an error without losing a large capacity memory when a memory error is detected in the kernel resident area.
According to one preferred embodiment, a memory controller of the present invention is used for a storage device for forming interleave groups by dividing each of a plurality of memory banks into sub-banks and then combining sub-banks belonging to different memory banks, and the memory controller generates addresses in the banks of a plurality of memory banks so as to form an interleave within each of the interleave groups in accordance with the address of the storage device. In the memory controller, when a memory error is occurred in any one of the interleave groups, the interleave group having the memory error is interchanged with another interleave group so as to generate the address.
REFERENCES:
patent: 4823252 (1989-04-01), Horst et al.
patent: 5659713 (1997-08-01), Goodwin et al.
patent: 5684973 (1997-11-01), Sullivan et al.
patent: 0239299 (1987-03-01), None
patent: 55-032188 (1980-03-01), None
patent: 55-052600 (1980-04-01), None
patent: 61-020164 (1986-01-01), None
patent: 62-002339 (1987-01-01), None
patent: 64-017128 (1989-01-01), None
patent: 64-076341 (1989-03-01), None
patent: 1-111246 (1989-04-01), None
patent: 5-006305 (1993-01-01), None
patent: 10-301842 (1998-11-01), None
Cabeca John W.
NEC Corporation
Peugh Brian R.
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Memory controller for interchanging memory against memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory controller for interchanging memory against memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller for interchanging memory against memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2509165