Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-01-15
2001-04-03
Decady, Albert (Department: 2133)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S100000, C714S763000
Reexamination Certificate
active
06212631
ABSTRACT:
BACKGROUND
The present disclosure relates generally to computer systems, and more particularly, to error correction of cache memory with respect to main memory.
In the field of high speed computing, processor speed is generally limited by memory performance. For example, the CPU executes instructions at a predetermined rate. Similarly, main memory performs read and write operations at a second predetermined rate which is typically less than one order of magnitude slower than the CPU execution rate. In other words, the access time of main memory is insufficient to keep up with the CPU. Thus, during the execution of memory access instructions, CPU performance will degrade to the memory access rate. The CPU must wait for memory to complete its cycle on every instruction execution.
It is possible to construct a special-purpose memory which has a cycle-time approximately equal to that of the CPU's instruction cycle time. Unfortunately, such memories are far more expensive than typical semiconductor memories and are generally not feasible as a total primary memory solution. Accordingly, many computer systems compromise by constructing a relatively small cache of this high speed memory while retaining the slower semiconductor memory as the primary memory.
The cache is managed under hardware control to maintain a copy of a portion of the main memory which is likely to be used by the CPU. Thus, as long as the CPU only accesses those memory locations maintained in the cache, the CPU will execute at close to full speed. Of course, it is inevitable that the CPU will occasionally attempt to read a memory location not contained in the cache. During these misses, the data are retrieved from main memory and stored in the cache. Therefore, CPU performance degrades to the main memory access rate during misses, but the overall speed of the processor is enhanced by the use of the high speed cache.
Use of the cache memory is not free from complications. Data consistency problems can arise by using a cache to store data that also appear in the primary memory. For example, data which is modified by the CPU and stored in the cache is necessarily different from the data stored at that same memory location in the primary memory. Generally, various methods of ensuring data consistency are employed, for example: a write-through method, a dirty-bit method, and with the use of error correction code hardware, also referred to as error checking and correcting (ECC) hardware. These various methods are known in the art and only briefly mentioned herein.
In the operation of high-speed computers, it is thus frequently advantageous to employ a high speed cache memory with a CPU. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses ECC to ensure the integrity of the data delivered between the cache and main memory.
Some computer users desire high reliability, while others desire maximum performance. Their preference is apparent for example, by their selection of ECC or non-ECC memory (e.g., DRAM) in a respective initial system configuration. In addition, currently available BIOS (basic input output system) for Intel® based motherboards offer a setup option for L2 Cache ECC as either ON or OFF. A default setting for the L2 Cache ECC (i.e., either ON or OFF) is typically chosen by a computer manufacturer installing such a motherboard into a computer system. Any change to the opposite state, from ON to OFF or from OFF to ON is up to the user. Enabling ECC in either one or both of the cache or the DRAM causes a noticeable performance hit.
While the selection of ECC or non-ECC DRAM is an option offered to the customer at order time, the choice of ECC or non-ECC L2 cache enabling is buried in the BIOS settings for the respective computer motherboard. Most users will not readily realize that the settings for ECC or non-ECC L2 cache exists in the BIOS setup. The computer user typically uses the factory default setting for L2 cache ECC. If the default for L2 cache ECC is OFF, then an improved performance will be gained. However, if L2 cache ECC is ON, then an increased reliability of single bit error correction in the L2 cache subsystem will be gained. However, if a system user desires a maximum performance and the default for L2 cache ECC is ON, then the maximum performance will not be obtained. Similarly, if the user desires a high system reliability and the default for L2 cache ECC is OFF, then the high system reliability will not be obtained.
With respect to DRAM ECC, detection and configuration of system DRAM ECC is accomplished via the BIOS (basic input output system). That is, a function in the BIOS detects whether system DRAM is capable of ECC. Since DRAM having ECC capability carries with it a cost premium, it is assumed that a computer user wants memory ECC enabled if memory ECC is present.
On computer systems which employ L2 cache ECC, a BIOS setup screen is typically provided, the set-up screen providing an option for enabling and disabling the L2 cache ECC, either on or off, respectively. The user is expected to select a preference. In any case, a default must be decided open, sacrificing either performance or reliability.
An improved method and apparatus for the enabling/disabling of L2 cache ECC is thus desired. In addition, it is also desired to overcome a problem of non-optimal usage of error checking and correcting within a computer system.
SUMMARY
According to one embodiment of the present disclosure, a computer system includes at least one microprocessor having an L2 cache, at least one memory, and basic input output system (BIOS) firmware. The L2 cache includes error checking and correcting capability (ECC). The at least one memory includes either all ECC capable memory or any combination of ECC capable and non-ECC capable memory. Lastly, the BIOS firmware includes an L2 cache support feature, wherein the L2 cache support feature includes three user-selectable options. The three options include i) L2 cache ECC ON, ii) L2 cache ECC OFF, and iii) L2 cache AUTO. L2 cache ECC ON is for enabling L2 cache ECC. L2 cache ECC OFF is for not enabling L2 cache ECC. Lastly, L2 cache ECC AUTO is for automatically enabling or not enabling L2 cache ECC in response to a detection of the presence of a) all ECC capable memory or b) any combination of ECC and non-ECC capable memory, respectively.
A technical advantage of the present embodiments is that an optimal performance or an optimal reliability can be obtained with a computer system having L2 cache ECC capability, wherein enabling of L2 cache ECC capability is automatically aligned with that of ECC capable memory or other ECC capable component.
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System Management BIOS Reference Specification, Version 2.2
Armstrong Anthony
Springer David Scott
Zucker Brian Todd
De'cady Albert
Dell USA L.P.
Haynes and Boone L.L.P.
Torres Joseph
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