Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-10-04
2001-08-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S597000, C438S618000, C438S637000
Reexamination Certificate
active
06274468
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87110883, filed Jul. 6, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a contact. More particularly, the present invention relates to a method of manufacturing a borderless contact.
2. Description of Related Art
Conventionally, when an inter-layer dielectric (ILD) layer is patterned to form a contact opening, border strips around the periphery of the contact are normally reserved according to the design rules. Thus, even when the contact opening is misaligned, undesirable leakage current can be prevented.
Nowadays, due to the high level of integration of semiconductor devices, line width has shrunk to around 0.25 &mgr;m and below. Therefore, the newer generation of contacts is fabricated according to a borderless design concept that minimizes area occupation of each device.
However, when a borderless contact opening is patterned, occurrence of any misalignment diminishes contact area between the source/drain region and the contact. In other words, contact resistance between a contact and the source/drain region will rise. In a serious situation, contact may be formed in a position so far from the source/drain region that an open circuit condition arises.
FIGS. 1A through 1D
are cross-sectional views showing the progression of manufacturing steps in producing a borderless contact according to a conventional method.
First, as shown in
FIG. 1A
, a device isolation structure
101
, for example, shallow trench isolation, is formed over the substrate
100
. The device isolation structure
101
marks out the main active area in which a device is to be formed. Next, a gate structure
102
is formed on the substrate
100
and source/drain regions
110
are formed in the substrate
100
. The gate structure
102
comprises a gate oxide layer
104
, a gate conductive layer
106
and a cap layer
108
. In addition, spacers
112
are formed on the sidewalls of the gate structure
102
. The source/drain regions
110
have lightly doped drain (LDD) structures. Preferably, the LDD structures are formed by first carrying out an ion implantation using the gate structure
102
as a mask to form lightly doped source/drain regions. Then, another ion implantation is performed using the spacers
112
as masks to form the heavily doped source/drain regions.
Next, as shown in
FIG. 1B
, a dielectric layer
116
is formed over the substrate
100
and covers at least the entire gate structure
102
. The dielectric layer
116
can be, for example, a silicon oxide layer formed by a chemical vapor deposition (CVD) method. Thereafter, the dielectric layer
116
is planarized so that a thickness roughly equal to the height of the subsequently formed contact remains. The dielectric layer
116
can be planarized using, for example, a chemical-mechanical polishing (CMP) method.
Next, as shown in FIG.
1
C. conventional photolithographic and etching processes are used to pattern the dielectric layer
116
, in which processes contact openings that ought to expose the source/drain regions
110
are formed. However, due to the misalignment of the patterned dielectric layer
116
a
, contact openings
117
and
119
are offset from the position where source/drain regions
110
are formed. In serious situations, as shown in
FIG. 1C
, the contact opening
117
exposes the cap layer
108
and spacer
112
of the gate structure
102
while the contact opening
119
exposes a portion of the device isolation structure
101
.
Next, as shown in
FIG. 1D
, contacts
118
and
120
are formed inside the respective contact openings
117
and
119
within the insulating layer
116
a
. In general, the contacts
118
and
120
are formed by first depositing a glue/barrier layer (not shown in
FIG. 1D
) that is conformal to the contact openings
117
and
119
. The glue/barrier layer is formed so that the adhesive strength between the subsequently deposited conductive layer and other material layers is enhanced. Thereafter, a conductive layer (also not shown in FIG.
1
D), for example, a tungsten layer, is deposited over the substrate
100
and fills the contact openings
117
and
119
. Finally, the conductive layer is removed to expose the insulating layer
116
a
, thereby forming contacts
117
and
119
inside the contact openings
118
and
120
respectively. The conductive layer can be removed using a chemical-mechanical polishing (CMP) method, for example.
In the aforementioned processing operation, contacts
118
and
120
are unable to make contact with the source/drain regions
110
as required due to severe misalignment when the dielectric layer
116
is patterned to form openings
117
and
119
. an open-circuit condition is established, which results in device malfunction.
In light of the foregoing, there is a need to improve the method of manufacturing borderless contact.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of manufacturing a borderless contact that is capable of forming sufficient contact area for coupling a contact with a source/drain region even though the via opening for forming the contact is seriously misaligned relative to the source/drain region.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing borderless contact. The method includes several steps. First, a substrate is provided that has a gate structure formed thereon. The substrate has source/drain regions and spacers on the sidewalls of the gate structure. Thereafter, an insulating layer conformal to the substrate profile is formed above the substrate. Then, a portion of the insulating layer is removed so that the remaining isolating layer at least covers the gate structure and the source/drain regions. Next, a dielectric layer having openings is formed over the insulating layer, and then a portion of the insulating layer at the bottom of the openings is removed to expose the source/drain region, thereby forming contact openings. Finally, conductive material is deposited into the contact openings to form contacts that electrically couple with the respective source/drain regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5118382 (1992-06-01), Cronin et al.
patent: 5654231 (1997-08-01), Liang et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5811357 (1998-09-01), Armacost et al.
patent: 5899742 (1999-05-01), Sun
Huang Jiawei
J.C. Patents
Meier Stephen D.
United Microelectronics Corp.
Vockrodt Jeff
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