Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-21
2001-04-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000, C257S513000, C257S516000, C257S532000, C438S210000, C438S228000, C438S239000, C438S252000, C438S394000, C438S439000
Reexamination Certificate
active
06215142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an analog semiconductor device capable of preventing step between transistor and capacitor regions and a method of fabricating the same.
2. Description of the Related Art
In general, an analog semiconductor device stores information in various states, while a digital semiconductor device stores information in only two states, LOW and HIGH. The analog semiconductor device includes a resistor and capacitor at each node of its circuit. Since the resistance and capacitance vary with voltage, a resistor having a specific value is required.
FIG. 1
shows a cross-sectional view for describing a method of fabricating a conventional analog semiconductor device. Referring to
FIG. 1
, field oxide layers
2
are formed on a semiconductor substrate
1
by a well-known LOCOS(LOCal Oxidation of Silicon), to define a transistor region A and an analog capacitor region B. A gate insulating layer
3
, a first doped polysilicon layer
4
, a tungsten silicide layer
5
are then deposited on the overall substrate
21
in sequence and patterned, so that a gate
100
a
is formed on the substrate
21
of the transistor region A and a lower electrode
100
b
of a capacitor is formed on the field oxide layer
2
of the analog capacitor region B. On the lower electrode
100
b
, are then formed a polysilicon layer for buffer
6
and an oxide layer
7
acting as a dielectric layer. In case bonds between fluorine(F) gas of the tungsten silicide layer
5
and O
2
gas are formed, the polysilicon layer for buffer
6
prevents capacitance decrease due to thickness variation of the oxide layer
7
. Thereafter, an upper electrode
8
of the capacitor is formed on the oxide layer
7
, thereby forming an analog capacitor
200
. Here, the upper electrode
8
is formed to a second doped polysilicon layer. When patterning the gate
100
a
and the upper electrode
8
, ARC layers
9
are formed on the tungsten silicide layer
5
and the second doped polysilicon layer, respectively.
However, as described above, since the analog capacitor
200
is formed on the field oxide layer
2
, a step occurs between the transistor region A and capacitor region B. Owing to this step, the metal interconnection lines are opened when forming them and notching occurs when performing photolithography, thereby deteriorating reliability and yield of the device. Furthermore, these problems occur especially in devices under submicron.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions.
Furthermore, it is another object of the present invention to provide a method of fabricating the analog semiconductor device capable of preventing step between transistor and capacitor region.
To accomplish one object of the present invention, an analog semiconductor device according to the present invention, includes : a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; a gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.
Furthermore, to accomplish another object of the present invention, an analog semiconductor device according to the present invention, is fabricated as follows. Firstly, a mask pattern for a low electrode of a capacitor is formed to expose a portion of the substrate. An oxide ion-implantation layer is then formed in the substrate by ion-implanting oxide ions at a first energy. Thereafter, an impurity ion-implantation layer of a high concentration is formed over the oxide ion-implantation layer by ion-implanting impurity ions of the high concentration at a second energy being lower than the first energy. The mask pattern is removed and the substrate of a resultant structure is annealed, to form an oxide layer in the substrate and form a lower electrode of a capacitor on the oxide layer, the lower electrode being made of a diffusion layer of the high concentration. Thereafter, isolating layers of trench-type are formed in the substrate to define a transistor region and a capacitor region, respectively, the capacitor region having the oxide layer and the lower electrode. An insulating layer and a conductive layer for a gate are formed on the overall substrate, sequentially and patterned to form a gate insulating layer and gate on the substrate of the transistor region and simultaneously form a dielectric layer and an upper electrode of the capacitor on the lower electrode of the capacitor region.
In an embodiment of the present invention, annealing is performed to temperature of 900 to 1,100° C.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4912055 (1990-03-01), Min et al.
patent: 4970174 (1990-11-01), Min et al.
patent: 5053350 (1991-10-01), Solomon
patent: 5187566 (1993-02-01), Yoshikawa et al.
patent: 5281835 (1994-01-01), Tomita et al.
patent: 5378919 (1995-01-01), Ochiai
patent: 5397729 (1995-03-01), Kayanuma et al.
patent: 5670410 (1997-09-01), Pan
patent: 5723375 (1998-03-01), Ma et al.
patent: 5780333 (1998-07-01), Kim
patent: 05095263 (1993-04-01), None
patent: 06252345 (1994-09-01), None
patent: 06318673 (1994-11-01), None
Cha Myung Hwan
Lee Jae Dong
Hyundai Electronics Industries Co,. Ltd.
Ladas & Parry
Wojciechowicz Edward
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