Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-09-12
1999-05-11
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518519, 36518526, 36518527, 36518533, G11C16/04
Patent
active
059034998
ABSTRACT:
A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.
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Ho Ming-Chou
Lee Jian-Hsing
Peng Kuo-Reay
Yeh Juang-Ke
Ackerman Stephen B.
Knowles Billy J.
Nelms David
Nguyen Vanthu
Saile George O.
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