Method of forming contact

Details Method of forming contact Method of forming contact

1998-10-28

2001-01-02

Nelms, David (Department: 2812)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S533000

Utility Patent

active

06169016

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of forming bit-line contacts and node contact using a thin doped polysilicon layer.
2. Description of the Related Art
Modern semiconductor fabrication technique in a very large scale integration (VLSI) highly increases the circuit density on a chip. The increase in circuit density causes the downsizing of devices and increases device packing density. Recently, enhanced resolution of photolithography technique, for example, using phase shifting masks and self-aligning processes have all been advantageous to downsizing devices and increasing density. Minimum device size is smaller than one micrometer and there are over a million transistors on a chip in ultra large scale integration (ULSI). However, as technology develops towards an even higher circuit density, some problems develop in semiconductor fabrication. One such problem high resistivity due to a short distance between a bit line contact and a node contact in a dynamic random access memory (DRAM).
In
FIGS. 1A
to
1
D, a conventional method of forming a bit line contact and a node contact is shown.
FIG. 1A
illustrates formation of metal oxide semiconductors formed on a semiconductor substrate
100
. The metal oxide semiconductors comprise gates
110
a
and
110
b
, a source/drain region
112
a
between the gates
110
a
, and source/drain regions
112
b
between the gates
110
a
and
110
b
. Each of the gates
110
a
and
110
b
respectively includes a first doped polysilicon layer
102
with a thickness of about 1000 Å on the bottom of the gates
110
, a first tungsten silicide layer
104
with a thickness of about 1000 Å on the first doped polysilicon layer
102
, a silicon nitride layer
106
with a thickness of about 1500 Å on the first tungsten silicide layer
102
, and a spacer
108
formed around the first doped polysilicon layer
102
, the tungsten silicide layer
104
and the silicon nitride layer
106
. The material of the spacer
108
is silicon nitride which can protect the gates
110
a
and
110
b.
FIG. 1B
illustrates deposition of a second doped polysilicon layer
114
with a thickness of about 1000 Å on the gates
110
a
and the source/drain regions
112
a
. Then, a second tungsten silicide layer
116
with a thickness of about 1000 Å is deposited on the second doped polysilicon layer
114
. The second tungsten silicide layer
116
and the second doped polysilicon layer
114
are converted to a bit line contact
117
by a photolithography step.
FIG. 1C
illustrates deposition of a dielectric layer
118
on the gates
110
a
and
110
b
, the bit line contact
117
, and the semiconductor substrate
100
. A photosensitive pattern (not shown) is defined on the dielectric layer
118
. Then, the dielectric layer
118
not covered by the photosensitive pattern is etched anisotropically to form a via opening
120
on the source/drain regions
112
b
and to expose the top surface of the source/drain regions
112
b.
FIG. 1D
illustrates deposition of a third doped polysilicon layer
122
with a thickness of about 6000-10000 Å on the dielectric layer
118
. The third doped polysilicon layer
122
fills the via opening
120
. Part of the third doped polysilicon layer
122
is removed to form a node contact
120
a
to the source/drain region
112
b
by photolithography and etching, A hemi-spherical grain (HSG) layer
124
is formed on the surface of the node contact
120
a
salient to the dielectric layer
118
. Then, a thin ONO film
125
is formed on the HSG layer
124
. A fourth doped polysilicon layer
126
with a thickness of about 1000 Å is deposited and etched over the ONO layer
125
.
The line width of the bit line contact and of the node contact formed by a conventional technique satisfies process requirements. The RC delay tome can be decreased by inhibiting bit line sheet resistance and resistivity of the bit line contact and of the node contact from the first, second, third and fourth doped polysilicon layers
102
,
114
,
122
and
126
. However, when the lien width achieves 0.25 &mgr;m or less for highly integrated circuits and the width of the bit line contact and of the node contact is 0.1 &mgr;m, resistivity of these contacts is till high, Furthermore, a thin oxide film is naturally formed on the substrate surface, the oxide film prevents polysilicon deposited in the contacts from adequately making contact with the substrate. So conventional methods obviously cannot satisfy process requirements. Developing a technique which can provide lower resistivity of bit line contacts and node contacts is of great importance for the industry.
SUMMARY OF THE INVENTION
It is therefor the major object of the invention to provide an improved contact method of forming contacts. The contacts provided from this invention increases contact sheet resistance to satisfy process requirements. Furthermore, the method of forming contacts not only enhances conductivity by increasing mobile carriers in the contacts, but also destroys the naturally formed thin oxide layer in the substrate surface. This enhances the contact between the polysilicon and the substrate.
The invention achieves the above-identified objects by providing a method of forming contacts, wherein the contacts comprises bit line contact and node contacts. First, a substrate is provided. Gates are formed on the substrate, and source/drain regions are formed in the substrate. Each gate comprises a first polysilicon layer, a tungsten silicide layer, a silicon nitride layer and a spacer formed around these layers. Then, a second polysilicon layer with a thickness of about 22-400 Å is deposited on the substrate and the gates. An ion implantation with an energy of about 20-30 Kev is performed to dope ions with a concentration of about 2E15-4E15 into the second polysilicon layer. A third doped polysilicon layer and a tungsten silicide layer are deposited sequentially on the second polysilicon layer. The second polysilicon layer, the third polysilicon layer and the tungsten silicide layer are partially removed by etching to form a bit line contact to a source/drain region between gates. A dielectric layer with a thickness of about 5000 Å is deposited over the entire surface. A via opening to another source/drain region adjacent to the bit line contact is formed by etching the dielectric layer after chemical mechanical polishing (CMP). A fourth polysilicon layer with a thickness of about 200-400 Å and comprising a dopant with a concentration of about 2E15-4E15 is deposited with an energy of about 20-30 Kev. A fifth doped polysilicon layer with a thickness of about 6000-10000 Å is deposited on the fourth polysilicon layer. The fourth and fifth polysilicon layers are partially removed to form a node contact to the source/drain region adjacent the bit line contact by photolithography and etching. Furthermore, a HGS layer, an ONO layer and a sixth polysilicon layer are formed on the node contact surface by a conventional technique.


REFERENCES:
patent: 5341014 (1994-08-01), Fujii et al.
patent: 5510296 (1996-04-01), Yen et al.
patent: 5589415 (1996-12-01), Blanchard
patent: 5652183 (1997-07-01), Fujii

Affiliated with

Also associated with

Rating

Method of forming contact does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming contact will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2507902