Method for producing insulated gate thin film semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S152000, C438S160000

Reexamination Certificate

active

06204099

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention disclosed in the specification relates to a method for producing a semiconductor device having a gate electrode using a crystalline thin film semiconductor, for example, a thin film transistor (TFT). As application of the TFT, an active matrix type liquid crystal display device has been known. This display device performs a fine and high resolution display by arranging a TFT as a switching element in each of several hundred thousands or more pixels disposed at a matrix form.
2. Description of the Related Art
Recently, a transistor using a thin film semiconductor formed on a glass or quartz substrate, such as a thin film transistor (TFT) has been concerned. A thin film semiconductor having a thickness of several 100 to several 1000 Å is formed on a surface of a glass substrate or a quarts substrate, and then the transistor (insulated gate field effect transistor) is formed using the thin film semiconductor.
Of such the TFT, a TFT using an amorphous silicon film and a TFT using a crystalline silicon film is used in practice.
Since the TFT using the crystalline silicon film has a superior characteristic, it has a great future.
In the TFT using a crystalline silicon semiconductor, the crystalline silicon thin film is obtained by a method for thermal-annealing an amorphous silicon film, or a method for forming a crystalline silicon film directly using a vapor phase growth method. However, in order to perform the process at a low temperature, a photo-annealing for crystallizing an amorphous silicon film by irradiating an intense light such as a laser has been proposed. (for example, Japanese Patent Application Open No. 4-37144)
There are two methods roughly as a case wherein crystalline silicon film is obtained by photo-annealing includes. In a first method, photo-annealing is performed after etching a semiconductor thin film into a shape of an element to be formed. In a second method, after photo-annealing for an even (flat) film is performed, the film is etched into a shape of an element to be formed. In general, it has known that the element obtained by the first method has a superior characteristic (field effect mobility) than that obtained by the second method. This may be because in the first method, the film is contracted by photo-annealing, and thus a central portion of a pattern is stressed, thereby increasing crystallinity of the film.
However, there is a problem in this case. That is, although an initial characteristic is good, by use for a long period of time, the characteristic is deteriorated largely.
A cause that the characteristic is deteriorated by the conventional method will be explained with
FIGS. 3A
to
3
D. Initially, an island semiconductor region
31
of amorphous silicon having a rectangle
32
is formed as shown in FIG.
3
A. When photo-annealing is performed, the film is contracted slightly by crystallization. A dot line of the figure represents a size of the island semiconductor region before the photo-annealing. In this contract process, a region
33
that distortion is accumulated in an outermost portion of the island semiconductor region
31
is formed. The crystallinity of such the region
33
is not high so much. (
FIG. 3B
)
In a case wherein a gate electrode
34
is formed across such the island region (FIG.
3
C), in an (a-b) cross section (
FIG. 3D
) along the gate electrode, the region
33
that distortion is accumulated is to be formed under the gate electrode
34
and a gate insulating film
35
. When a voltage is applied to the gate electrode
34
, since an interface characteristic between the region
35
and the gate insulating film is not good, charges are trapped, so that deterioration occurs by a parasitic channel or the like due to the charges. (
FIG. 3D
)
SUMMARY OF THE INVENTION
The object of the present invention is to prevent such the deterioration, and to provide a method for producing an insulated gate semiconductor device having less deterioration.
According to a first aspect of the present invention, the following processes are obtained.
(1) An amorphous semiconductor film is etched into a first shape that a width of a narrowest portion is 100 &mgr;m or less, to form an island semiconductor region.
(2) The semiconductor region is photo-annealed to crystalize it or to increase the crystallinity thereof.
(3) Of end portions (or peripheral portions) of the semiconductor region, at least a gate electrode or a channel forming region of a semiconductor device is etched by 10 &mgr;m or more from ends, to form a semiconductor region having a second shape.
Also, according to a second aspect of the present invention, the following processes are obtained.
(1) An amorphous semiconductor film is etched into a first shame that a width of a narrowest portion is 100 &mgr;m or less, to form an island semiconductor region.
(2) The semiconductor region is photo-annealed to crystalize it or to increase the crystallinity thereof.
(3) At least a part of end portions (or peripheral portions) of the semiconductor region is etched.
(4) An gate insulating film is formed to cover the semiconductor region.
(5) An gate electrode is formed across the etched portion of the end portions of the semiconductor region.
(6) An N-type or P-type impurity is introduced or diffused using the gate electrode as a mask.
In the first and second aspects of the present invention, the first shape is one of a rectangle, a regular polygon and an ellipse (including a circle), and generally it is preferred that a shape does not include a concave portion at any point on a periphery.
In the above structure, an amorphous silicon film is formed on a substrate having an insulating surface, such as a glass substrate or a quartz substrate by plasma chemical vapor deposition (plasma CVD) and low pressure thermal CVD. In photo-annealing, various excimer lasers such as a KrF excimer laser (wavelength of 248 nm) and a XeCl excimer laser (wavelength of 308 nm), and a Nd:YAG laser (wavelength of 1064 nm) and a second harmonic component (wavelength of 532 nm) and a third harmonic component (wavelength of 355 nm) may be used. In the present invention, a light source may pulse-oscillate or continuous-oscillate. As disclosed in Japanese Patent Application Open No. 6-318701, in photo-annealing, crystallization may be promoted using a metal element (for example, Fe, Co, Ni, Pd or Pt) which promotes crystallization of silicon.
The present invention disclosed in the specification is effective in a case wherein an island semiconductor region is constructed in a single-crystalline region or a region equivalent to the single-crystalline region. As described later, the single-crystalline region or the region equivalent to the single-crystalline region can be obtained by scan-irradiating a linearly processed laser light into an amorphous silicon film and a crystalline silicon film.
The single-crystalline region or the region equivalent to the single-crystalline region is defined as a region that the following conditions are satisfied.
(1) The region does not contain substantially crystal boundary.
(2) The region contains hydrogen or a halogen element to neutralize a point defect at a concentration of 1×10
15
to 1×10
20
atoms cm
−3
.
(3) The region contains carbon or nitrogen at a concentration of 1×10
16
to 5×10
18
atoms cm
−3
.
(4) The region contains oxygen at a concentration of 1×10
17
to 5×10
19
atoms cm
−3
.
The above concentrations are defined as a minimum value of a measurement value measured by secondary ion mass spectrometry (SIMS).
In the present invention disclosed in the specification, only a channel portion is etched so as not to be adjacent to a channel that influences characteristics of a semiconductor device. This corresponds to that etching is performed so as not to remain such a region in a portion which crosses a gate electrode.
FIGS. 1A
to
1
D show a basic structure of the present invention. A plurality of island amorphous semiconductor region

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