Passivation of sidewalls of a word line stack

Details Passivation of sidewalls of a word line stack Passivation of sidewalls of a word line stack

1999-08-18

2001-03-06

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S230000, C438S297000, C438S303000, C438S305000, C438S592000, C438S595000, C257S623000

Reexamination Certificate

active

06198144

ABSTRACT:

BACKGROUND
The present invention relates generally to semiconductor devices and, more particularly, to the fabrication of word line stacks.
During the manufacture of some integrated circuits, field effect transistor (FET) gate electrodes and gate electrode interconnects are etched from a thick conductive layer that covers other circuitry. For example, in semiconductor memory circuits, wherever a word lines passes over a field oxide region, it functions as a gate electrode interconnect; wherever the word line passes over a gate dielectric layer overlying an active region, the word line functions as a gate electrode.
In early generations of integrated circuits, gate electrodes and electrode interconnects were often etched from a heavily-doped polycrystalline silicon (polysi) layer. However, fast operational speeds and low stack heights that are desirable for some applications could not be obtained using the polySi layer. Faster operational speeds, for example, are required for certain high-speed processor and memory circuits. Reduced stack heights are desirable for increasing the planarity of the integrated circuit to obtain better photolithographic resolution. To achieve increased operational speeds and lower stack heights in subsequent generations of integrated circuits, it became necessary to reduce the sheet resistance of the conductive layer from which the gates and gate interconnects were formed. A significant improvement in the conductivity of gate electrodes and gate interconnects was obtained by forming a low-resistance metal silicide layer on top of the electrode/interconnect layer.
A silicide is a binary compound formed by the reaction of a metal and silicon (Si) at an elevated temperature. Refractory metal silicides, for example, include a refractory metal, such as tungsten (W) or titanium (Ti), and have relatively high melting points in the range of about 1,400 degrees Celsius (° C.) to greater than about 3,400° C. Metals with a high melting point are preferred for structures, such as gates, that are created early in the fabrication process because the processing of integrated circuit typically involves a series of steps performed at elevated temperatures. In contrast, a metal layer formed at the end of the fabrication process need not have a particularly high melting point. Thus, aluminum (Al), which has a melting point of only about 660° C., generally is used only for the upper level interconnect lines and is applied to the circuitry only after no further processing of the wafer above about 600° C. is required. Although metal silicides have significantly higher conductivity than heavily-doped polySi, a silicide is about an order of magnitude more resistive than the pure metal from which it is formed.
To improve the properties of gates and gate interconnects even further, integrated circuit manufacturers are investigating the use of pure metal layers. Tungsten, for example, is of particular interest because it is relatively inexpensive, has a high melting point (approximately 3,410° C.), and is known to be compatible with current manufacturing techniques.
The use of unreacted tungsten metal as a conductive word line layer can create certain problems during the fabrication process of the integrated circuit. The word line materials often must be capable of withstanding high temperature processing in an oxidizing environment. For example, shortly after the word line stack is patterned, a source/drain reoxidation is performed to repair damage that occurs to the gate oxide near the corners of source and drain regions as a result of etching the word line. The source/drain reoxidation reduces the electric field strength at the gate edge by upwardly chamfering the edge, thereby reducing the “hot electron” effect that can cause threshold voltage shifts. However, during such a reoxidation process, exposed tungsten along the edges or sidewalls of the stack is converted quickly to tungsten trioxide gas at high temperatures in the presence of oxygen. Moreover, sub-limation of the tungsten oxide is not self-limiting. The oxidation of the tungsten layer as well as oxidation of the barrier layer degrades the electrical properties of the word line. Accordingly, passivation of the exposed edges or sidewalls of the tungsten layer and the barrier layer is desirable.
Various techniques have been proposed for passivating the sidewalls of the word line stack prior to reoxidation of the gate dielectric. However, some of the proposed techniques are not easily integrated into standard device fabrication processes, while other techniques do not result in sufficient reoxidation of the gate dielectric in a sufficiently short period of time.
SUMMARY
In general, techniques are disclosed for passivating exposed surfaces of a word line stack such as sidewalls of a metal layer or a conductive barrier layer to help prevent conversion of those layers to a non-conductive compound during a subsequent oxidation process.
According to one aspect, a method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls. Subsequently, a reoxidation process is performed with respect to the gate dielectric.
According to another aspect, a word line stack is formed over a gate dielectric. Forming the word line stack includes forming a polysilicon layer on the gate dielectric and forming a metal layer above the polysilicon layer. Nitride spacers are formed along portions of sidewalls of the word line stack adjacent the metal layer. At least lower portions of sidewalls of the polysilicon layer are not covered by the nitride spacers. Subsequently, a reoxidation process is performed.
Various implementations include one or more of the following features. Forming the nitride spacers can include forming a nitride layer over the wafer, and etching the nitride layer to form the nitride spacers. The nitride layer can be formed, for example, by chemical vapor deposition, and etching the nitride layer can include performing an anisotropic etch such as reactive ion etch process.
Prior to forming the nitride spacers, an oxide layer can be formed adjacent the lowermost portions of the sidewalls of the stack. The oxide layer can be formed, for example, using a high density plasma process, a collimated sputtering process or a flowfill technique. Such techniques can be advantageous in forming an oxide which is thicker on horizontal surfaces of the wafer than on vertical surfaces, such as the sidewalls of stack. In some implementations, an isotropic etch is used to remove portions of the oxide layer so as to expose the sidewalls of the metal layer and/or the conductive barrier layer prior to forming the nitride spacers.
Following formation of the nitride spacers, a portion or substantially all of the oxide formed on the horizontal surfaces can be removed prior to performing the reoxidation. The oxide can be removed from the horizontal surfaces, for example, using a selective wet etch.
According to another aspect, an integrated circuit includes a semiconductor wafer and a gate dielectric film disposed on a surface of the wafer. A gate electrode stack, which includes multiple layers, is disposed on the gate dielectric film. Nitride spacers extend along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls.
Some implementations include a polysilicon layer on the gate dielectric film and a metal layer above the polysilicon layer with the spacers extending along sidewalls of the metal layer. The stack also can include a conductive barrier layer between the polysilicon layer and the metal layer, with the spacers extending along sidewalls of the barrier layer as well. In some situations, the spacers have a thickness in the range of about 50 Å to about 500 Å.
One or more of the following advantages are present in some implementations. By providing the nitride spacers along the exposed surfaces of the metal layer and/or

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