Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-01-07
2001-06-12
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C709S215000, C710S120000
Reexamination Certificate
active
06247100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an improved multiprocessor system and, in particular, to a method and system for transmitting address commands in multiprocessor system. Still more particularly, the present invention relates to a method and system for transmitting address commands in a multiprocessor system comprising multiple nodes interconnected by an address bus which is controlled by a switch.
2. Description of the Related Art
A conventional symmetric multiprocessor data processing system (SMP) may include a number of processors that are each coupled to a shared system bus. Each processor may include on-board cache that provides local storage for instructions and data, execution circuitry for executing instructions, and a bus interface unit (BIU) that supports communication across the shared system bus according to a predetermined bus communication protocol. Typically, in SMP systems, bus devices (i.e. processors, memory controller or I/O hubs) are connected via electronically isolated busses. When one device has a data transfer request for transferring data to another device, a switch, or other interprocessor interconnection medium routes the data from the source device to the correct destination device.
a multiprocessor system, the functional characteristics of the interprocessor interconnection medium are a significant constraint on system performance. Characteristics sought in the medium include fast access arbitration, fair arbitration (i.e. no unit is starved for access), independence of connections (i.e. a connection between some units does not constrain connections between other units), deadlock prevention, equal opportunity for a processor to send and receive, and modular growth capability.
Typically, in a switching bus structure, information that is needed by a requesting device may be required to move across multiple busses to reach the requesting device. A further need in multi-bus switching is snooping cache associated with each processor in order to maintain cache coherency. One method for handling information moving across multiple busses is buffering or queuing the information at each switching point within the switching bus structure. However, address commands that are queued will stay en route longer than necessary, resulting in interference between commands. In practice, the interference causes address commands to need to be retried or cancelled, wasting a significant amount of bandwidth along with increasing the latency of moving an address command to the requesting device.
In view of the foregoing, a method for transmitting address commands across multiple busses in a switching bus structure is needed wherein the latency of transmitting address commands is reduced and wherein information is not queued at multiple switches.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to provide an improved multiprocessor system.
It is another object of the present invention to provide an improved method and system for transmitting address commands in multiprocessor system.
It is yet another object of the present invention to provide an improved method and system for transmitting address commands in a multiprocessor system comprising multiple nodes interconnected by an address bus which is controlled by a switch.
In accordance with the method and system of the present invention, a request for arbitration of an address bus is transmitted from a controller within a node of multiple nodes to an arbitration switch, which controls transmission across the address bus. The address command is transmitted from the controller to the arbitration switch, in response to receiving a grant of arbitration of the address bus. The address command is then broadcast from the arbitration switch to a controller within each node of multiple nodes, in response to receiving the address command at the arbitration switch. The address command is broadcast from the controller within each node, in response to receiving the broadcast address command at the controller within each node, such that all address command transmissions on the address bus are transmitted to each processor within a multiprocessor system.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Drehmel Robert Allen
Haselhorst Kent Harold
Hoover Russell Dean
Marcella James Anthony
Bracewell & Patterson LLP
Dillon Andrew J.
International Business Machines - Corporation
Moazzami Nasser
Yoo Do Hyun
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