Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-09-22
2001-08-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S233100, C365S230030, C365S230080
Reexamination Certificate
active
06272056
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor integrated circuit device employing the semiconductor memory device. In particular, the invention relates to a semiconductor memory device capable of implementing efficient redundancy-based repair when any defect occurs in a memory cell, and to a semiconductor integrated circuit device employing such a semiconductor memory device.
2. Description of the Background Art
As a semiconductor memory device capable of processing a large amount of data at a high speed, a memory chip is now being developed having a logic circuit and a DRAM (Dynamic Random Access Memory) both mounted on one chip (hereinafter referred to as “embedded DRAM”). While data is conventionally transferred between a logic circuit represented by a processor (MPU) and a memory portion represented by the DRAM via an I/O pin and a data bus, the embedded DRAM aims to enhance data transfer rate (access speed and memory band width) between its processor and DRAM by transferring data via a memory bus mounted on the memory chip.
Concerning a semiconductor memory device having a large scale memory cell array, a redundancy-based repair scheme is important in order to enhance yield in manufacture. By the redundancy-based repair (hereinafter referred to simply as redundancy repair), a defective portion of a memory cell generated in manufacture is repaired using a spare memory cell in a redundant circuit that is preliminary mounted on the same chip.
Although the data transfer rate between the logic portion and the memory portion can be improved in the embedded DRAM, the logic circuit and the memory circuit mounted on the same chip considerably limit the layout, and thus it is an object of the embedded DRAMI to enhance the degree of integration relative to both of the circuits.
A fuse element is used for programming a defective address in the redundancy repair scheme. The fuse element occupies a relatively large area which is inappropriate for enhancement of integration, and thus significantly influences the layout design. If the same redundant circuit is shared by a plurality of banks for reducing the number of fuse elements, a large number of switching circuits are required for transferring data between data I/O lines and the redundant circuit in input and output of data, leading to limitation of layout.
In order to achieve an object of reducing the layout area, which is one of the important objects for the embedded DRAM, it is highly important to efficiently arrange a redundant circuit.
For execution of the redundancy repair, a redundancy judgement is first made by comparing an input address signal with a defective address stored in a fuse element and determining if they match with each other. An actual access operation is then carried out by determining an address to which an access is to be made. Accordingly, an additional cycle is required for the redundancy judgement each time the access operation is done. In the embedded DRAM aiming to achieve enhanced-speed data processing, it is important to make the redundancy judgement more efficiently in relation to the timing to reduce the time necessary for the judgement and thus improve the operating speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device such as an embedded DRAM having a large scale memory cell array, in which redundancy-based repair can be implemented efficiently in relation to layout and operating speed when any defect occurs in a memory cell.
The present invention is generally related to a semiconductor integrated circuit device including a logic circuit and a memory circuit.
The logic circuit generates a clock signal, an address signal and a command signal to transmit and receive a data signal.
The memory circuit performs a reading operation and a writing operation for the data signal in response to activation of the command signal according to the address signal, and includes a memory cell array having a plurality of normal memory cells arranged in rows and columns, a redundant circuit for replacing a normal memory cell having a defect, and an address decode circuit receiving the address signal and generating an address decode signal for selectively activating one of rows and one of columns of the normal memory cells corresponding to the address signal in response to activation of the clock signal.
The memory circuit further includes a redundancy control circuit receiving the address signal in response to activation of the clock signal to make a redundancy judgement and issue an instruction for effecting a redundancy-based repair operation when the address signal is associated with an address of the defective normal memory cell, a redundant decode circuit in response to result of the redundancy judgement for performing the redundancy-based repair operation, and an address latch circuit receiving and latching the address signal transmitted from the logic circuit in response to preceding activation of the clock signal before the command signal is activated, and transmitting the address signal to the address decode circuit and the redundancy control circuit.
A semiconductor memory device according to another aspect of the invention operates in synchronization with a clock signal to transmit and receive a data signal in response to an address signal and a command signal. The semiconductor memory device includes an input terminal, a mode decode circuit, an address latch circuit, a memory cell array, a redundant circuit, a redundancy control circuit, an address decode circuit, a redundant decode circuit, and a drive circuit.
The input terminal receives the clock signal, the address signal, the command signal, and an address mode signal for designating a timing at which the address signal is entered (hereinafter referred to as “enter timing”). The mode decode circuit defines the enter timing of the address signal as either one of a first address mode and a second address mode in response to the address mode signal. The address latch circuit receives and latches the address signal from the input terminal at an activation timing of the clock signal if the first address mode is designated, and receives and latches the address signal from the input terminal at the activation timing of the clock signal while the command signal is activated if the second address mode is designated. The memory cell array includes a plurality of normal memory cells arranged in rows and columns. The redundant circuit includes a plurality of spare memory cell rows and spare memory cell columns for replacing a normal memory cell having a defect. The redundancy control circuit receives the address signal transmitted from the address latch circuit to make a redundancy judgement, and issues an instruction for effecting a redundancy repair operation if the address signal corresponds to an address of the defective normal memory cell. The address decode circuit generates an address decode signal for selectively activating one of rows of the normal memory cells and one of columns of the normal memory cells in response to the address signal transmitted from the address latch circuit. The redundant decode circuit selectively activates one of spare memory cell rows and spare memory cell columns in response to activation of the clock signal if the redundancy repair operation is carried out. The drive circuit selectively activates one of rows and one of columns of the normal memory cells corresponding to the address decode signal in response to the activation of the clock signal.
A semiconductor memory device according to still another aspect of the invention operates synchronously with a clock signal to read or write a data signal in response to a row address signal and a column address signal. The semiconductor memory device includes a memory cell array having normal memory cells arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks arranged in a first number of r
Auduong Gene N.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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