Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-09
2001-07-24
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000, C257S908000
Reexamination Certificate
active
06265739
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a non-volatile semiconductor memory device having a double-layer gate structure which includes a gate insulating film, a floating gate layer as a charge storing layer, an insulating film, and a control gate layer. It also relates to a method for manufacturing the device. More particularly, the invention relates to a structure which includes gate insulating films and gate electrodes incorporated in a memory cell section and its peripheral circuit section.
Non-volatile semiconductor memory devices each comprise a memory cell (a memory cell transistor), a select transistor, and a peripheral circuit including a transistor of a high breakdown voltage (Vpp) and a transistor operable with a normal power Vcc (the transistors of the peripheral circuit will hereinafter be referred to as “peripheral circuit transistors”). These transistors have gate insulating films of different thicknesses corresponding to voltages applied thereto.
FIGS. 36A
,
36
B and
FIGS. 37A and 37B
are sectional views, illustrating the conventional steps of manufacturing a nonvolatile semiconductor memory device. As is shown in
FIG. 36A
, N-well regions
302
and P-well regions
303
are formed in a silicon substrate
301
, and then sufficiently thick element isolating films
304
are formed by the LOCOS method. Element regions isolated by the element isolating films
304
include, for example, a memory cell section, a select transistor (select Tr), and transistors incorporated in a memory peripheral circuit, such as a high breakdown voltage transistor (Vpp Tr) and a normal power transistor (Vcc Tr). First, a gate oxide film
305
is formed for the select Tr. Then, resist is coated and patterned, thereby covering the region other than a memory cell section with a resist layer
315
, removing the gate oxide film
305
and forming a gate oxide film
306
for the memory cell section. In
FIGS. 36 and 37
, each gap indicates that the memory cell and the select Tr, Vpp Tr and Vcc Tr show different sections.
Referring then to
FIG. 36B
, a polysilicon layer
307
as a first layer is deposited on the resultant structure and then patterned. Thereafter, an insulating film
308
is formed on each of the patterned polysilicon layers. The polysilicon layers
307
serve as the floating gate of the memory cell and the gate electrode of the select transistor. On the transistor (Vpp Tr, Vcc Tr) side of the peripheral circuit, the insulating film
308
, the polysilicon layer
307
as the first layer, and the gate insulating film
305
below the layer
307
are removed. Thereafter, the resist is patterned, thereby forming a gate oxide film
309
in the Vpp Tr section. Further, another resist layer
316
is patterned as shown in
FIG. 36B
, thereby removing the gate oxide film
309
in the Vcc Tr section.
Subsequently, as shown in
FIG. 37C
, a gate oxide film
310
is formed in the Vcc Tr section, and then a polysilicon layer (gate electrode)
311
as a second layer is formed. Thereafter, the memory cell section and each transistor section are patterned, ion implantation is performed, an interlayer insulating film
312
is deposited, and wiring layers
313
are formed. Thus, a memory cell, a select transistor, a high breakdown voltage transistor and a Vcc transistor are formed as shown in FIG.
37
D.
In the above-described structure, the four gate oxide films
305
,
306
,
309
and
310
of the transistors are formed in different steps. Therefore, a great number of resist forming steps, oxidation steps, etc. are required, resulting in an increase in manufacturing cost.
Moreover, as described above, in the non-volatile semiconductor memory device having a memory cell section of a double-layer gate structure consisting of a floating gate layer (first polysilicon layer
307
) and a control gate layer (second polysilicon layer
311
), the gate electrodes of the transistors in the peripheral circuit are usually realized by the use of the control gate layer (second polysilicon layer
311
) in the memory cell section. If in this case, surface-channel type N-channel and P-channel MOS transistors are formed as the transistors of the peripheral circuit, the following difficulties will occur:
In general, the control gate layer of a memory cell transistor has a polycide structure formed by depositing, for example, WSi (tungsten silicide) on the second polysilicon layer to increase the conductivity. Then, the control gate layer is coated with resist and then patterned into a gate electrode.
In the conventional method using the control gate layer as the gates of the transistors of the peripheral circuit, it is necessary before the deposition of WSi to correctly implant each of N-type and P-type impurities into the second polysilicon layer, in order to form N-channel and P-channel MOS transistors of surface-channel type suitable for integration. Then, it is necessary to deposit WSi, and to correctly implant each of N-type and P-type impurities into regions which will serve as source and drain regions, after the gate electrode is formed. Thus, the step of patterning resist and the step of implanting impurities must be repeated.
If, on the other hand, the gate electrodes of the transistors of the peripheral circuit are formed of the first polysilicon layer
307
which will serve as the floating gate layer of the memory cell, a surface-channel type element can be obtained by implanting, into the gate electrode, an impurity of the same conductivity as that of an impurity implanted in the source and drain regions, after the gate electrode is formed. In this case, however, the high speed operation of the transistors of the peripheral circuit cannot be realized, since the first polysilicon layer
307
as the floating gate layer usually has a higher resistance than the second polysilicon layer
311
as the control gate layer.
As explained above, in the conventional method, the transistors of the peripheral circuits have gate insulating films of different thicknesses, which inevitably increases the manufacturing steps and hence the manufacturing cost. To achieve high speed operation, the gate of each transistor of the peripheral circuit of the memory usually has the same polycide structure as the control gate layer of the memory cell section. If a surface-channel type element is realized by the transistor with the gate of the polycide structure, a great number of resist patterning steps and impurity implanting steps are required, thereby increasing the manufacturing cost.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in light of the above circumstances, and is aimed at providing a non-volatile semiconductor memory device which can be manufactured by a small number of steps, and a method of manufacturing the device. The invention is also aimed at providing a non-volatile semiconductor memory device which can be manufactured by a small number of steps and operate at a high speed in a highly reliable manner, and a method for manufacturing the device.
According to a first aspect of the invention, there is provided a non-volatile semiconductor memory device comprising: a plurality of memory cell units each including at least one memory cell formed by stacking a charge storing layer and a control gate layer above a semiconductor substrate in which data is programmed and erased by charging and discharging the charge storing layer; a plurality of select transistors each connected to a corresponding one of the memory cell units; and first and second transistors each for controlling a voltage to be applied to at least one of the memory cells and the select transistor connected thereto, the first transistor having a first gate insulating film, and the second transistor having a second gate insulating film with a different thickness from the first gate insulating film, wherein a gate insulating film incorporated in the memory cell, a gate insulating film incorporated in the select transistor and the first gate insulating film are formed of substantially the same film.
In the non-vola
Aritome Seiichi
Shimizu Kazuhiro
Yaegashi Toshitake
Hogan & Hartson L.L.P.
Kabushiki Kaisha Toshiba
Saadat Mahshid
Wilson Allan R.
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