Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-01-14
2001-06-26
Bragdon, Reginald G. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S149000, C700S094000, C704S500000, C709S213000
Reexamination Certificate
active
06253293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention in general to data processing and in particular, to methods for utilizing shared memory in a multiprocessor system.
2. Description of the Related Art
The ability to process audio information has become increasingly important in the personal computer (PC) environment. Among other things, audio support is an important requirement for many multimedia applications, such as gaming and telecommunications. Audio functionality is therefore typically available on most conventional PCs, either in the form of an add-on audio board or as a standard feature provided on the motherboard itself. In fact, PC users increasingly expect not only audio functionality but high quality sound capability. Additionally, digital audio plays a significant role outside the traditional PC realm, such as in compact disk players, VCRs and televisions. As the audio technology progresses, digital applications are becoming increasingly sophisticated as improvements in sound quality and sound effects are sought.
One of the key components in many digital audio information processing systems is the decoder. Generally, the decoder receives data in a compressed form and converts that data into a decompressed digital form. The decompressed digital data is then passed on for further processing, such as filtering, expansion or mixing, conversion into analog form, and eventually conversion into audible tones. In other words the decoder must provide the proper hardware and software interfaces to communicate with the possible compressed (and decompressed) data sources, as well as the destination digital and/or audio devices. In addition, the decoder must have the proper interfaces required for overall control and debugging by a host microprocessor or microcontroller. Since, there are a number of different audio compression/decompression formats and interface definitions, such as Dolby AC-3 and S/PDIF (Sony/Phillips Digital Interface), a state of the art digital audio decoder should at least be capable of supporting multiple compression/decompression formats.
In almost any streaming data processing application, such as digital audio decompression, maintaining data throughput is essential. Often, the incoming data is organized in blocks, frames or similar data structures. Thus, in streaming data processing applications, efficient handling of structured data is many times crucial for high speed processing and consequently data throughput. A need therefore has arisen for methods of exchanging blocks or frames of data between processing blocks within a given device or system, such as an audio decoder, operating on streams of structured data.
SUMMARY OF THE INVENTION
According to the principles of the present invention, a method of operating shared memory in a multiple processor system is disclosed. A default token is maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is already accessing the shared memory. The token is transferred to the second processor if the first processor is not accessing to the shared memory the second processor.
The principles of the present invention allow at least two processor in a multiprocessor system to efficiently access shared memory. These principles can be utilized in many applications, and in particular to those applications where blocks of structured data are being processed. One exemplary application is in multiple processor audio decoders, where streams of data are received in blocks and frames which are subsequently accessed first by one processor the resulting blocks passed to the second processor for further processing.
REFERENCES:
patent: 5057998 (1991-10-01), Hirokawa
patent: 5418913 (1995-05-01), Fujimoto
patent: 5491771 (1996-02-01), Gupta et al.
patent: 5497373 (1996-03-01), Hulen et al.
patent: 5768613 (1998-06-01), Asghar
Divine James
Dokic Miroslav
Luo Zheng
Niehaus Jeffrey
Rao Raghunath
Bragdon Reginald G.
Cirrus Logic Inc.
Lin, Esq. Steven
Murphy, Esq. James J.
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