Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-27
2001-01-30
Ng{circumflex over (o)}, Ng{circumflex over (a)}n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S349000
Reexamination Certificate
active
06180985
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a silicon-on insulator(SOI) device and a method for fabricating the same, and more particularly to a SOI device and a method for fabricating the same capable of obtaining the stable operation performance.
With high integrity and high performance of semiconductor devices, the semiconductor integration technology using SOI wafer instead of single crystal Si wafer being comprised of a bulk silicon has been proposed. It is because the devices fabricated into the SOI wafer have advantages of high speed due to low junction capacitance, low voltage driving due to low threshold voltage and decrease in latch-up due to complete device isolation as compared with those fabricated in the single crystal Si wafer.
The SOI wafer has a stack structure of a silicon substrate for supporting means, a silicon layer for providing a device formation region and a buried oxide layer for a bonding medium sandwiched between the silicon substrate and the silicon layer. There are a separation by implanted oxygen (SIMOX) method and a bonding method as a SOI wafer fabrication method.
FIG. 1
is a sectional view illustrating a SOI device in the prior art. A SOI wafer
10
having a stack structure of a silicon substrate
1
, aburied oxide layer
2
and a silicon layer
3
is prepared. An isolation layer
4
is formed in the silicon layer
3
to define a device formation region. The isolation layer
4
is contacted with the buried oxide layer
2
to provide a complete isolation. A gate
6
including a gate oxide
5
is formed over the device formation region of the silicon layer
3
defined by the isolation layer
4
by a conventional process. A source region
7
and a drain region
8
are formed in the device formation region of the silicon layer
3
to be contacted with the buried oxide layer
2
. A portion of the silicon layer between the source region
7
and the drain region
8
is a channel region
9
.
In the SOI device, the junction regions such as source and drain regions
7
and
8
are contacted with the buried oxide layer
2
and the depletion region below the junction regions are removed, so that the capacitance in the junction region is reduced and it accomplishes the high speed of the device.
However, the prior SOI device has a poor operation performance due to floating body effect. That is, the body of a transistor formed in the SOI wafer floats from the silicon substrate and the charges are accumulated in the channel region below the gate in operation of the transistor. The operation performance of the transistor becomes unstable due to the accumulated charges.
On the other hand, soas toprevent floatingbody effect, a region for connecting the body of the transistor to a ground terminal for supplying a substrate bias, is formed in the SOI device. A predetermined voltage is applied from the ground terminal to the channel region and it prevents the charges from accumulating the channel region in the transistor operation. However, because the prior method has need of additional dimension for forming the region for connecting the body of the transistor to the ground terminal in every unit cell, it is not applicable to the high integration device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a SOI device and a method of fabricating the same capable of obtaining the stable operation performance.
According to an aspect of the present invention, there is provided to a SOI device, comprising: a SOI wafer having a stack structure of a silicon substrate, a buried oxide layer having a first and a second contact holes and a silicon layer; an isolation layer formed in the silicon layer to define a device formation region; a transistor including a gate formed over the device formation region of the silicon layer defined by the isolation layer, source and drain regions formed at the both side of the gate in the device formation region and a channel region which is a portion of the device formation region between the source and drain region; a conduction layer being contacted with the buried oxide layer; an impurity region for well pick-up formed in the silicon layer to be contacted with the buried oxide layer; a first contact layer formed within the first contact hole of the buried oxide layer to electrically connect the channel region of the transistor and the conduction layer; and a second contact layer formed within the second contact hole of the buried oxide layer to electrically connect the impurity region for well pick-up and the conduction layer.
There is also to provide a method for fabricating a silicon on insulator (SOI) device, comprising the steps of: preparing a silicon substrate; forming a conduction layer in the silicon substrate; forming a buried oxide layer having a first and a second contact holes on the silicon substrate including the conduction layer; forming a first and a second contact layers within the first and the second contact holes in the buried oxide layer, respectively to contact with the conduction layer; forming a silicon layer over the buried oxide layer including the first and the second contact layers; forming an isolation layer in the silicon layer to define a device formation region; forming a gate on the device formation region of the silicon layer over the first contact layer; forming a source region and a drain region at the both side of the gate in the device formation region and forming an impurity region for well pick-up formed in the silicon layer to be contacted with the second contact layer.
REFERENCES:
patent: 5608252 (1997-03-01), Nakato
patent: 5892256 (1999-04-01), Matsushita et al.
patent: 5945712 (1999-08-01), Kim
patent: 6072217 (2000-06-01), Burr
Hyundai Electronics Industries Co,. Ltd.
Ladas & Parry
Ng{circumflex over (o)} Ng{circumflex over (a)}n V.
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