Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-04-06
2001-07-17
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C438S737000, C438S740000, C438S745000
Reexamination Certificate
active
06261960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing semiconductor devices containing conductive line and conductive via interconnection structures. More specifically, this invention relates to a dual damascene method of manufacturing semiconductor devices containing conductive line and conductive via interconnection structures. Even more specifically, this invention relates to a dual damascene method of manufacturing semiconductor devices having high-density rectangular cross-section contacts that avoids the effects of mask misalignment during manufacturing.
2. Discussion of the Related Art
As the prices of semiconductor devices continue to plummet, more components and more complex components are incorporated into devices to extend their performance and functionality and thus to maintain their price and profitability. However, increased performance and functionality requires greater density and increased transistor counts, which in turn requires more interconnections and increased layers to accommodate the increased number of interconnections.
Traditional etchback methods to provide interconnection structures include a single damascene method. Although the single damascene method offers the advantage of improved planarization, it is however, time consuming in that it requires numerous processing steps. Also, an interface film is required between the conductive via and conductive wiring, which increases the via resistance and lowers the performance of the device.
Another cost reduction method is to build the device in the shortest time and with the fewest process steps as possible. The reduction in process steps also reduces random killer defects on the wafer resulting in higher yields. One such technique to reduce process steps is the employment of a dual damascene technique in which both the conductive via plugs and the conductive wiring line is filled in a single process step after the conductive vias and conductive wire trenches cavities have been made. The excess conductive material is then removed by using one of several well-known processes, such as the CMP (chemical mechanical polishing) process. The dual damascene technique is an improvement over the single damascene technique because it permits the filling of both the conductive lines and conductive vias with metal at the same time, with only one interface film, thereby eliminating process steps and at the same time decreasing overall contact/via resistance.
IBM developed the dual damascene technique. See, for example, Joshi, “A New Damascene Structure for Submicrometer Interconnect Wiring,” IEEE Electron Letters, vol. 14, No. 3, March 1993, pages 129-132; and Kaanta et al., “Dual Damascene: A ULSI Wiring Technology,” Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152. The use of a damascene technique wherein the dielectric is planarized by chemical-mechanical polish is discussed in Kenny et al., “A Buried-Plate Trench Cell for a 64-Mb DRAM,” 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 14 and 15. U.S. Pat. No. 5,262,354 discloses a three-step method of forming electrical conductive vias and lines involving a damascene technique to create lines on a substrate and, in addition, this patent discloses the advantages of chemical-mechanical polishing with aluminum slurry in dilute nitric acid to planarize a dielectric surface. U.S. Pat. No. 5,093,279 discloses a laser ablation damascene process for planarizing metal/polymer structures in the fabrication of both interlevels via metallization and circuitization layers in integrated circuit interconnects.
The dual damascene technique involves the simultaneous formation of a structure comprising a conductive via and a conductive line, thereby requiring fewer manipulative steps than the single damascene technique and eliminating the interface between the conductive via and conductive line, which is necessarily formed by the single damascene technique.
Although dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages. One disadvantage is that the typical dual damascene technique requires two masking steps to form the pattern, the first masking delineates the dimensions and shape of the conductive vias and the second masking step delineates the dimensions and shape of the conductive lines or vice versa. These two masking steps require critical alignment to position the conductive via within the dimensions of trenches in which the conductive lines are formed. It is highly desirable to have the length dimension of the conductive via extend the full width dimension of the conductive line. However, because that would require more critical alignment of the two masks, the conductive via length dimension is typically designed to be slightly smaller than the width dimension of the conductive line in the standard dual damascene process. Therefore, conductive lines are typically designed to be wider than the width dimension of the conductive vias in order to correct for alignment errors during manufacture. The requirement to have wider conductive lines results in a density reduction in a fixed silicon area. This suggests that the conductive vias are being printed at the minimum printable size while the lines are being printed larger than the minimum printable size. This results in the feature size not being laid out to maximize density efficiency per given surface area, thus requiring more layers of multi-level interconnection. All these factors negatively impact cost, yield and cycle time.
In addition, because the conductive vias are being printed at the minimum printable size and as is well known in the semiconductor manufacturing art, even though the mask (chrome) for the vias are square, because of lithographic techniques, the actual vias (resist pattern) have a circular cross-section because the comers of the vias become rounded. This rounding of the comers can result in a round via and the round via having a given diameter “d” has a cross-sectional area that is less than the cross-sectional area of a square via having the same length and width dimension “d”. The reduced cross-sectional area of the round via has an increased resistance at the interface between the round conductive via and the conductive wire.
Therefore, what is needed is an improved dual damascene technique that produces a rectangular cross-sectional interface between a conductive via and a conductive line and that provides the conductive via width to extend the full dimension of the conductive line and no further in order to achieve the maximum electrical contact between the conductive line and the conductive via and to achieve the greatest density possible in the semiconductor device.
DISCLOSURE OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are attained by a method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via.
In accordance with an aspect of the invention, a first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities that are simultaneously filled with a conductive material.
In accordance with another aspect of the invention, the first layer of photoresist is patterned with a dimension X that is a dimension of the conductive lines and conductive vias. The second layer of photoresist is patterned with a dimension X+a, where the dimension “a” is selected to compensate for a misalignment of the first layer of photoresist and to compensate
Rangarajan Bharath
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices Inc
Nelson H. Donald
Powell William
LandOfFree
High density contacts having rectangular cross-section for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High density contacts having rectangular cross-section for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density contacts having rectangular cross-section for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2503058