Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1998-06-08
2001-06-12
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S400000, C713S502000
Reexamination Certificate
active
06247138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing signal generating circuit, a semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied and a signal transmission system and, more particularly, to a timing signal generating circuit aimed at increasing the speed of signal transmission between LSI (Large Scale Integration Circuit) chips or between a plurality of devices or circuit blocks within one chip.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has improved rapidly; in particular, the performance of dynamic random access memories (DRAMs) and processors has improved dramatically year by year.
Namely, processor performance has increased dramatically in terms of speed, whereas DRAM performance improvements have been dramatic primarily in terms of storage capacity. However, the improvement in DRAM speed has not been so dramatic as the increase in storage capacity, as a result of which a gap between the speed of DRAMs and that of processors has widened and, in recent years, this speed gap has been becoming a bottleneck in boosting computer performance.
Further, with increasing chip size, not only signal transmission between the chips but also the speed of signal transmission between devices and between constituent circuits (circuit blocks) within one LSI chip (semiconductor integrated circuit device) is becoming a major limiting factor in chip performance.
On the other hand, if the speed of signal transmission between LSI chips is to be extremely increased, for example, it is required that signal receiving circuits be made to operate with correct timing to the signals, and techniques such as DLL (Delay Locked Loop) and PLL (Phase Locked Loop) have been known for addressing this requirement.
In addition, the need has arisen for high-speed signal transmission between LSI chips, for example, between a DRAM and a processor (logic circuit), or between a plurality of devices or circuit blocks within one LSI chip. There is, therefore, a need for a timing signal generating circuit that can generate with simple circuitry and with high accuracy a plurality of timing signals, having prescribed phase differences, synchronous with a reference clock.
Furthermore, with increasing operating speeds of LSIs, there is also a need for a signal transmission system that can perform large-capacity signal transmission at high speed between LSIs and between apparatuses constructed with a plurality of LSIs.
The prior art and the problems associated with the prior art will be described in detail later with reference to drawings.
SUMMARY OF THE INVENTION
An object of a first aspect of the present invention is to provide a semiconductor integrated circuit device that permits timing design with relatively high adjustment accuracy to be done in a short period. An object of a second aspect of the present invention is to provide a signal transmission system capable of high-speed, error-free signal transmission without being affected by skew on each signal line. An object of a third aspect of the present invention is to provide a timing signal generating circuit that can generate with simple circuitry and with high accuracy a plurality of timing signals, having prescribed phase differences, synchronous with a reference clock.
According to the present invention, there is provided a semiconductor integrated circuit device having a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core, wherein the timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle only for a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks.
The timing adjusting circuit may include a logic gate for enabling the generated DRAM control signal for output only for a period during which the control command is issued. The semiconductor integrated circuit device may include an MPU that accesses the DRAM. The timing adjusting circuit may include a first counter for counting the first clock; a second counter for counting the second clock; and a timing buffer circuit for generating the DRAM control signal by setting the control command active for a period starting from the time that the count value of the first counter reaches a first value and lasting until the time that the count value of the second counter reaches a second value.
The first counter and the second counter may be loop counters. At least, either one of the first and second counters may include a selection circuit for accepting multiple bit outputs from the counter, and for selecting one bit output out of the multiple bit outputs for output in accordance with a selection control input value; and a timing setting section for storing and outputting the selection control input value.
The timing setting section may be a register. The output of the timing setting section may be set before shipment in accordance with production process conditions. The output of the timing setting section may be set before shipment in accordance with required operating speed.
The timing adjusting circuit may include a common counter for counting one of the n clocks, or the reference clock, as a common clock; a first logic gate for enabling one of the n clocks for output only for a period during which the count value of the common counter shows a first value; a second logic gate for enabling one of the n clocks for output only for a period during which the count value of the common counter shows a second value; and a timing buffer circuit for generating the DRAM control signal by setting the control command active for a period starting from the time that the output of the first logic gate becomes active and lasting until the time that the output of the second logic gate becomes active.
The common counter may be a loop counter. The common counter may include a selection circuit for accepting multiple bit outputs from the counter, and for selecting one bit output out of the multiple bit outputs for output in accordance with a selection control input value; and a timing setting section for storing and outputting the selection control input value.
The semiconductor integrated circuit device may include a logic gate for supplying the common clock to the first counter only for a period during which the control command is issued. The command decoder may include a logic gate for enabling the first value indicated as the count value of the first counter for output to the timing buffer circuit only for the period during which the control command is issued.
The semiconductor integrated circuit device may include a selection circuit for selecting one of the n clocks in accordance with a selection control input value and for supplying the selected clock as a clock to the first logic gate or the second logic gate, and a timing setting section for storing and outputting the selection control input value. The timing setting section may be a register. The output of the timing setting section may be set before shipment in accordance with production process conditions. The output of the timing setting section may be set before shipment in accordance with required operating speed.
According to the present invention, there is also provided a timing adjusting circuit for generating n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and for generating a control signal by being set in an active state in a prescribed operation cycle only for a period starting at a first pred
Araki Hisakatsu
Gotoh Kohtaroh
Ogawa Junji
Tamura Hirotaka
Wakayama Shigetoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lee Thomas
Mai Rijue
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