Bitstream decoding apparatus

Details Bitstream decoding apparatus Bitstream decoding apparatus

2000-03-24

2001-04-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from mixed code formats

C341S067000, C341S106000

Reexamination Certificate

active

06222467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for processing a video signal, and more particularly, to a bitstream decoding apparatus which decodes a video signal compressed according to the Moving Picture Experts Group (MPEG) standard within one clock cycle and converts the compressed video signal into the form of symbols such as video parameters and discrete cosine transform (DCT) coefficients. The present application is based on Korean Patent Application No. 99-10061 which is incorporated herein by reference.
2. Description of the Related Art
Video bitstreams compressed and encoded under the MPEG
1
and MPEG
2
standards include a fixed length code, a variable length code, and variable length codes of zero run-length and an AC coefficient pair. In a video decoding apparatus, in order to decode the three types of codes mentioned above from a bitstream into processible form, the bitstream undergoes a process of bitstream decoding at an initial step of decoding. The operating speed of the bitstream decoder is mainly determined by how fast it decodes the run-length codes which account for most of the video data. Recently, development of digital television including high-definition television (HDTV) requires transmission of a considerably high-resolution picture, for example, a resolution of 1920×1080 pixels per picture.
To speed up the decoding of a video decoding apparatus, it is necessary to increase the speed of the bitstream decoder as well as of the operating clock frequency. However, a conventional bitstream decoder has problems in transmitting a high-resolution picture signal since it takes a long time to decode a fixed length code, a variable length code, and variable length codes of zero run-length and an AC coefficient pair.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a video bitstream decoding apparatus capable of decoding a fixed length code, a variable length code, and a variable length code of zero run-length and an AC coefficient pair within a single clock cycle in response to transmission of a high-resolution picture signal such as that used in a digital televisions.
Accordingly, to achieve the above objective, there is provided a bitstream decoding apparatus for performing the decoding operation within a single clock cycle which has a bitstream decoder for decoding a bitstream input from a storing unit, a control logic for monitoring the bitstream decoding, and a video processor for converting the decoded bitstream into displayable pixel values. In the bitstream decoding apparatus, the bitstream decoder includes a shifter for shifting the bitstream according to the input of a bitstream to be shifted, a variable length decoder for decoding the output from the shifter into symbol and code by referring to a code book, a fixed length decoder for extracting bits from the most significant bit of a symbol to the extent prescribed by the control logic based on the output of the shifter to position the extracted bits onto the least significant bit of the symbol, a zero-run & AC decoder for receiving the outputs of the shifter and the variable length decoder as an input and, if an escape code exists, to calculate the zero run and AC coefficient, otherwise to calculate an AC coefficient using a zero run and AC level decoded by the variable length decoder, a first multiplexer for selecting the outputs from the variable length decoder, the fixed length decoder and the zero-run & AC decoder according to the control of the control logic, a second multiplexer for selecting a bitstream (number of bits) to be shifted among a variable length bitstream from the variable length decoder, a fixed length bitstream from the control logic, or a 24-bit bitstream if an escape code of AC exists, and a first comparator for comparing the bitstream selected by the second multiplexer with a predetermined bitstream to generate a signal for reading the storing unit.


REFERENCES:
patent: 5642115 (1997-06-01), Chen
patent: 5956429 (1999-09-01), Burns
patent: 5990812 (1999-11-01), Bakhmutsky

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