Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-04-19
2001-09-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S051000, C365S063000
Reexamination Certificate
active
06295236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor memory of the random access type having data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundancy data lines. I/O lines (input/output lines) lead from the memory in groups.
In a typical architecture of a 64-Mbit DRAM, the memory area is divided into four quadrants each with a data width of 32 bits. The entire memory comprises 128 bits. The 32-bit-wide data buses of the quadrants are further subdivided into four groups each of 8 bits. The data lines of the data buses are configured such that they can be connected to input/output lines I/O leading from the memory.
Previous designs of DRAMs have been provided with at least one redundant data line per group or a complete redundant group. A group in this case comprises a number of data lines.
In the case of this design of redundancy within a group, interconnection between the groups is not provided. This approach has the disadvantage that the maximum possible number of data lines that can be replaced within the group corresponds to the number of redundant lines per group.
In modern semiconductor memories, in which advancing technology is leading to smaller and smaller structures, contamination or other disruptive parameters such as, for example, layer thickness fluctuations in the fabrication process constitute a cause of defects which extend over a plurality of data lines or memory cells.
Thus, an areal defect, a so-called cluster defect which extends over a plurality of bit lines or memory cells can cause the on-chip redundancy devices within the memory chip which are designed according to the prior art to rapidly come up against their limits. In the case of a cluster defect, the number of data lines that may be affected in a group may be more than the number of redundant lines available in the group. In such a case, the entire memory chip can no longer be used, resulting in a total failure.
Moreover, defects, and in particular including cluster defects, of the local data lines internal to the memory or of the data lines are not precluded even in the course of fabrication. As a result, whole groups of local data lines which are assigned to the defective data line fail and have to be replaced. In such a case, the system of redundancy data lines limited to a group fails completely.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor memory of the random access type with a bus system organized in two planes which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which a flexible assignment of the redundancy data lines to different groups is made possible, which assignment also enables redundancy data lines of different groups to be assigned to one or more groups.
With the above and other objects in view there is provided, in accordance with the invention, a random access semiconductor memory, comprising:
a memory cell array with a multiplicity of memory cells;
a plurality of data lines connectible to the memory cells in the memory cell array, the data lines being combined in groups and at least one of the groups or individual data lines of the groups being formed by redundancy data lines;
input/output lines leading from the memory in groups;
a bus system organized in two planes including a first plane and a second plane, the first plane having bus lines to be connected to all the input/output lines and to all of the data lines, and the second plane having a plurality of individual partial buses with bus lines to be connected between the data lines of at least two of the groups of data lines and the input/output lines of one respective group of input/output lines.
In other words, the invention provides for a bus system organized in two planes, the first plane being provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand, and the second plane having a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.
The invention thus proposes that all of the data lines of the memory shall be connected, or be kept able to be connected, to all of the input/output lines of the memory via the first and second planes of the bus system. What is advantageous in this case is that redundancy data lines, which may be formed by other data lines of the memory, of a plurality of groups located apart from one another can be assigned to one group, in order to replace defective data lines. The flexibility achieved in this case is limited only by the total number of redundant data lines.
In accordance with an added feature of the invention, switches are connected between the bus lines of the bus system and the data lines or The input/output lines. In this particularly preferred embodiment of the invention, the bus lines of the first or of the second plane of the bus system are connected to the data lines and to the input/output lines via switches. The advantage in this case is that the connection of a data line to an input/output line can be switched reversibly, as required, by a switch.
In a further preferred refinement of the invention, the switches are formed by a tristate buffer circuit (“tristate buffer”). The advantage of a tristate buffer circuit is that the connection can be switched reversibly, and that in the case of an unrequired connection (open), leakage currents or capacitive loads hardly occur.
In accordance with an alternative embodiment of the invention, the switches are irreversibly set elements.
In accordance with a preferred embodiment of the invention, it is provided that the switches are actuated by means of predetermined state values.
It is advantageous for the state values for actuating the switches to be held in a read-only memory integrated in the semiconductor memory. Accordingly, the read-only memory is formed by a programming device with elements (“fuses” and “antifuses”) that can be set irreversibly.
In a concomitant, particularly preferred refinement of the invention, the state values for actuating the switches are obtained after a function and redundancy test of the semiconductor memory has been carried out.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory of the random access type with a bus system organized in two planes, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5867439 (1999-02-01), Asakura et al.
patent: 6163863 (2000-12-01), Schicht
patent: 195 13 287 A1 (1996-10-01), None
Brox Martin
Pfefferl Karl-Peter
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
LandOfFree
Semiconductor memory of the random access type with a bus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory of the random access type with a bus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory of the random access type with a bus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2502247