Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
1999-08-05
2001-07-17
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S328000, C257S329000, C257S330000, C257S331000, C257S332000
Reexamination Certificate
active
06262470
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device and a method for making the same, and more particularly, to an insulated gate bipolar transistor (IGBT) having a trench-type insulated gate structure and a method for making the same.
2. Description of the Related Art
An IGBT, an insulated-gate type power semiconductor device has both the high-speed switching characteristics of a power MOSFET and the high-output characteristics of a BJT. Thus, recently, the IGBT has been increasingly used in power electronic devices such as inverters, converters, switching power suppliers, etc. In particular, a trench IGBT avoids the resistive component generated by the parasitic junction-type FET effect, which has been an obstacle to improved characteristics of planar IGBTs, because it has the small onresistance of a bipolar device.
FIG. 1
is a cross-sectional view of a conventional trench IGBT.
Referring to
FIG. 1
, an n-type high-concentration buffer layer
2
and an n-type low-concentration drift region
3
are sequentially formed on a p-type high-concentration semiconductor substrate
1
used as a collector area. A p-type base region
4
is formed on the upper surface of drift region
3
, and an n-type high-concentration emitter region
5
is formed on part of the upper surface of the base region
4
. A trench
6
is formed through the emitter region
5
and the base region
4
, on part of drift region
3
. A thin gate insulative layer
7
is formed on the inner wall of trench
6
. A gate electrode
8
, i.e., an impurity-doped polysilicon layer, is formed on gate insulative layer
7
. Meanwhile, an emitter electrode
9
is formed so as to be electrically connected to base region
4
and emitter region
5
. A collector electrode
10
is formed so as to be electrically connected to semiconductor substrate
1
.
In this trench IGBT, a channel region is formed on the side wall of trench
6
within base region
4
. That is, if a forward bias is applied to gate electrode
8
, the conductive type of the side wall of trench
6
within base region
4
is inverted to form a channel. An electron current flows from the emitter region
5
to the drift region
3
through this channel. The electron current acts as a base current of a pnp transistor formed by base region
4
, drift region
3
, and semiconductor substrate
1
. Corresponding to the electron current, a hole current flows from semiconductor substrate
1
to emitter electrode
9
via drift region
3
and base region
4
.
However, the most significant problem of such a trench IGBT is a latch-up phenomenon. That is, a parasitic pnpn thyristor structure exists even in the trench IGBT, this pnpn structure being comprised of the emitter region
5
, the base region
4
, the drift region
3
, and the semiconductor substrate
1
. A voltage drop occurs in the lower portion of the emitter region
5
due to the hole current (indicated by arrows) flowing from the semiconductor substrate
1
to the base region
4
through the drift region
3
. Thus, if the voltage difference between the base region
4
and the emitter region
5
increases to the extent (e.g., 0.7V) of conducting a pn junction (J
1
), the parasitic pnpn thyristor operates to cause a latch-up. When latch-up occurs, the device can no longer be controlled by a gate voltage, and the device may become destroyed due to the flow of excessive current.
SUMMARY OF THE INVENTION
It is another object of the present invention to provide a method for making the trench IGBT.
According to a trench insulated gate bipolar transistor provided to achieve the first object, a second conductive drift region and a first conductive base region are sequentially formed on a first conductive semiconductor substrate used as a collector region. A channel stop region for partially limiting the vertical movement of a carrier via a conductive channel is formed on a predetermined upper portion of the base region. A second conductive emitter region is formed on a predetermined upper portion of the channel stop region. Some portion directly contacts the base region without passing through the channel stop region. Thus, a conductive channel can be formed only on the base region directly contacting the emitter region. A gate insulative layer is formed through the emitter region, the channel stop region, and the base region on the inner wall of a trench formed in a predetermined portion of the drift region. A gate electrode is formed on the gate insulative layer to fill the trench. An emitter electrode is formed so as to be electrically connected to the emitter region; and a collector electrode is formed so as to be electrically connected to the collector region.
Preferably, the channel stop region, doped with first conductive impurities at an impurity concentration that is higher than the first impurity concentration, is terminated at a predetermined distance from the sidewall of the trench, and has a portion protriding so as to contact the sidewall of the trench. Also, it is preferable that the emitter region is a pole-shaped emitter region formed along the sidewalls of the trench. Here, preferably, the pole-shaped emitter region is connected to an adjacent pole-shaped emitter region.
To achieve the second object, there is provided a method of manufacturing a trench insulated gate bipolar transistor according to the present invention. In this method, a second conductive drift region is formed on a first conductive semiconductor substrate used as a collector region. A first conductive base region is formed on a predetermined upper area of the drift region. A trench is formed through the base region and contacting a predetermined portion of the drift region. The trench is filled by sequentially forming a gate insulative layer and a gate conductive layer on the inner wall of the trench. A channel stop region is formed on a predetermined upper area of the base region, the channel stop region being a first conductive type and having a higher impurity concentration than the base region, so as to be selectively formed along the trench near the trench. A second conductive emitter region is formed on a predetermined upper area of the channel stop region, so as to selectively and directly contact the channel stop region along the trench at a portion where the channel stop region has been formed and to selectively and directly contact the base region along the trench at a portion where the channel stop region is not formed. An emitter electrode and a collector electrode are formed so as to be electrically connected to the emitter region and the semiconductor substrate, respectively.
According to the present invention, the amount of voltage drop due to an electron current in an emitter region is increased by forming a channel stop region between the emitter region and a base region along one section of the trench. On the other hand, the amount of voltage drop due to a hole current in the lower portion of the emitter region is decreased by doping the channel stop region with a high concentration p-type impurities. Thus, latch-up can be prevented.
REFERENCES:
patent: 5324966 (1994-06-01), Muraoka et al.
patent: 5705835 (1998-01-01), Nishiura et al.
patent: 5751024 (1998-05-01), Takahashi
Kim Tae-Hoon
Lee Kyu-Hyun
Flynn Nathan
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Wilson Scott R.
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