Reducing waiting time jitter

Details Reducing waiting time jitter Reducing waiting time jitter

1998-11-02

2001-05-08

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S505000

Reexamination Certificate

active

06229863

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of telecommunications and, in particular, to reducing waiting time jitter in systems in which pulse stuffing is used to synchronize an asynchronous signal for transmission over a synchronous communication link.
BACKGROUND
When a connection is made through a telecommunications network, some portions of the connection may be asynchronous to the local clock of another portion or link of the connection. “Bit stuffing” techniques have been used to synchronize digital signals from an asynchronous link with a local clock of a synchronous link. These bit stuffing techniques selectively add bits to and/or subtract bits from frames of data to adjust the length of the frames for transmission over the synchronous link. Once synchronized, the digital signal can be conveniently switched or transmitted with other, similarly synchronized, digital signals.
One bit stuffing technique is positive stuffing, in which it is assured that the frequency of the synchronized data signal is equal to or greater than the highest possible frequency of the asynchronous data signal, and frequency differences are made up by the insertion of stuff bits. For example, an asynchronous DS
1
data signal has a frequency of 1.544Mb/s±75 b/s, and may be converted by positive stuffing into a synchronized data signal with a frequency of at least 1.544075Mb/s. Generally, a higher frequency than this is used for the synchronized data signal in order to enable waiting time jitter, which arises as a result of the stuffing process and has a frequency component equal to the stuffing frequency, to be subsequently filtered out from the synchronized data signal.
Even though this technique of positive stuffing has been effective for some time, it cannot be readily used in a so-called synchronous transmission network in which incoming asynchronous and synchronous data signals must be accommodated to produce an outgoing synchronized data signal having substantially the same frequency as the incoming synchronous data signals. Synchronous networks are becoming of increasing importance in the communication of data signals.
In a synchronous network, an incoming synchronous data signal is already synchronized to the correct frequency so that there is no need to provide a synchronizing arrangement for such a signal. An incoming asynchronous data signal, however, can have a frequency which is either lower or higher than the synchronized data signal frequency, and a synchronizing arrangement is required in order to effect positive or negative stuffing, respectively, to produce a synchronized data signal from the asynchronous data signal. Whereas positive stuffing comprises providing a stuff bit in the synchronized data signal to compensate for a relatively lower asynchronous data signal frequency, negative stuffing comprises using a ‘spare’ bit of the synchronized data signal for transmitting data to compensate for a relatively higher asynchronous data signal frequency.
With this positive
egative stuffing, the synchronized data signal has a waiting time jitter component at a frequency which is equal to the rate of positive or negative stuffing. The closer the asynchronous data signal frequency is to the synchronized data signal frequency, the lower will be the stuffing rate and hence the jitter component frequency, rendering it more difficult to filter out the jitter from the synchronized data signal. Using a phase-locked loop (PLL) to filter out jitter, the need to handle lower frequency jitter components results in the disadvantages of increased acquisition times, memory requirements, and latency.
In a bit stuffing synchronizing arrangement, this jitter component, referred to generally as “waiting time jitter,” has a frequency which is equal to the nominal rate of positive or negative stuffing. For example, if the tributary data is an asynchronous DS
1
bit stream having a nominal bit rate of 1.544 Mb/s and an actual bit rate which may be up to 75 b/s more or less than this, then the jitter component will have a frequency in the range from 0 to 75 Hz. The closer the asynchronous bit stream rate is to the nominal rate, the lower the frequency of the jitter component.
In a receiver to which the bit stream is ultimately transmitted, a dejittering phase locked loop (PLL) is provided to reduce jitter, but this generally has a lower cut-off frequency of at least about 3 Hz so that most jitter due to stuffing is not attenuated by this PLL. This gives rise to a significant problem in the handling of asynchronous digital bit streams in some synchronous networks. The cut-off frequency of the receiver PLL cannot be substantially reduced to avoid the problem because this would unacceptably increase the acquisition of the PLL and elastic storage requirements, and in any event this cut-off frequency would have to be reduced to 0 to handle all possible jitter frequency components.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for circuits and methods for reducing waiting time jitter in telecommunications networks.
SUMMARY OF THE INVENTION
The above mentioned problems with telecommunications networks and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Circuits and methods are described which reduce waiting time jitter by using, at a synchronizer/multiplexer, a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit or has a “fractional component.” This sub-bit comparison essentially measures the waiting time jitter and is used to adjust the threshold level so as to reduce at least the low frequency components of the waiting time jitter at the synchronizer/multiplexer before transmission to the desynchronizer/demultiplexer.


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