Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-14
2001-08-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S660000, C438S663000, C438S683000
Reexamination Certificate
active
06277735
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a refractory metal silicide layer, and more particularly to a method for forming a refractory metal silicide layer self-aligned in a scaled down MOS field effect transistor.
In recent years, the requirement for scaling down in vertical and lateral dimensions of semiconductor devices for realization of the high density integration has been on the increase. Sub-quarter micron size memory devices and logic devices, for example, in the range of 0.15-0.25 micrometers have been now required for ultra large scale integrated circuits. Such high density integration of the semiconductor devices requires lateral and vertical size scaling down of the semiconductor elements such as MOS field effect transistor. Reductions in gate length and source/drain diffusion layer width are required as a lateral scaling down as well as reduction in thickness of the layers provided in the semiconductor element is also required as a vertical scaling down. Such reductions in gate length and source/drain diffusion layer width as well as reduction in thickness of the layers in the semiconductor elements, however, result in increase of in resistance thereof whereby the issue of circuit delay due to the increased resistance thereof is raised. Reduction in resistance of the semiconductor device is an essential issue for obtaining high speed performances of the ultra large scale integrated circuits. It is preferable to utilize a metal silicide layer for reduction in resistance of the semiconductor device and for scaling down thereof. Particularly, a refractory metal silicide such as titanium silicide is more preferable. In order to selectively form a fine refractory metal silicide layer on a limited small area, there had been used a self-aligned silicide salicide technique. Particularly, this salicide technique is important for scaling down of the MOS field effect transistor with high speed performance.
In the light of the scaling down of the MOS transistor with high speed performance, it is preferable that the source/drain diffusion regions are shallow. The silicidation reaction of refractory metal with silicon appears in the surface of the source/drain diffusion regions underlying the refractory metal layer. Namely, the refractory metal silicide layer is formed in upper regions of the source/drain diffusion layers. If the junction depth of the source/drain diffusion regions is shallower than the depth of the bottom of the refractory metal silicide layer, this means entire parts of the source/drain diffusion layers are occupied and replaced by the refractory metal silicide layer whereby the silicide layer is made into contact with the silicon substrate. This causes a crystal defect which may cause a leakage of current. In order to prevent this, it is required that the refractory metal silicide layer be formed within upper region of the source/drain diffusion regions or shallower than the source/drain diffusion regions.
Accordingly, in order to realize a substantial scaling down of the semiconductor device such as MOS field effect transistors including refractory metal silicide layers, it is essential to form the refractory metal silicide layer extremely shallow or form an extremely thin refractory metal silicide layer.
One of the conventional methods for forming the MOS field effect transistor by use of the salicide technique is disclosed in the Japanese patent publication No. 3-65658 and will be described as follows.
With reference to
FIG. 1A
, a silicon substrate
101
was prepared. Field oxide films
102
were selectively formed by a local oxidation of silicon method on a surface of the silicon substrate
101
so as to define an active region surrounded by the field oxide films
102
. Further, an ion implantation of impurity into the active region was carried out to form channel stoppers. Subsequently, a thermal oxidation of silicon was carried out to form a gate oxide film
103
. A chemical vapor deposition method was carried out to form a polysilicon film having a thickness of
150
nanometers over an entire region of the substrate
101
. An n-type impurity such as phosphorus was doped into the deposited polysilicon film so as to reduce a resistivity of the polysilicon film. The impurity doped polysilicon film was then patterned by a photolithography to form a gate electrode
104
. A chemical vapor deposition was carried out to deposit a silicon oxide film on an entire region of the substrate
101
. The deposited silicon oxide film was then subjected to an anisotropic etching to form side wall oxide films
105
at opposite sides of the gate electrode
104
. An ion-implantation of arsenic into the substrate
101
was carried out and then the substrate
101
was subjected to a heat treatment at a temperature of about 800-1000° C. to cause a diffusion of the doped impurity whereby source/drain regions
106
were formed.
With reference to
FIG. 1B
, a titanium film
107
having a thickness of about 50 nanometers was deposited by a sputtering method on an entire region of the substrate
101
.
With reference to
FIG. 1C
, the substrate
101
was subjected to a lamp anneal in a nitrogen atmosphere at a temperature of 600-650° C. for 30-60 seconds whereby a silicidation reaction of titanium with silicon appeared on interfaces of the titanium film
107
to the polysilicon gate electrode
104
and to the silicon diffusion layers
106
acting as the source/drain regions. As a result, C
49
structured titanium silicide layers
109
having a resistivity of about 60 &mgr;&OHgr; cm were formed on the interfaces of the titanium film
107
to the polysilicon gate electrode
104
and to the silicon diffusion layers
106
.
With reference to
FIG. 1D
, the nitrogen containing titanium film
110
was removed by a wet etching which uses a chemical in which hydrogen peroxide is mixed in an ammonia solution so as to leave only the C
49
structured titanium silicide layer
109
over the polysilicon gate electrode
104
and over the source and drain diffusion regions
106
.
With reference to
FIG. 1E
, the substrate
101
was subjected to a secondary heat treatment in an argon atmosphere at a temperature of 850° C. for 60 seconds to cause a phase transition of the C
49
structured titanium silicide layer
109
into a C
54
structured titanium silicide layer
111
having a resistivity of 20 &mgr;&OHgr; cm. The C
54
structured titanium silicide layer
111
has a lower resistivity than the C
49
structured titanium silicide layer
109
, for which reason a sheet resistance of the titanium silicide layer is reduced by the secondary heat treatment.
Another of the conventional methods for forming the MOS field effect transistor by use of the salicide technique is disclosed in the Japanese patent publication No. 3-73533 and will be described as follows.
With reference to
FIG. 2A
, a silicon substrate
101
was prepared. Field oxide films
102
were selectively formed by a local oxidation of silicon method on a surface of the silicon substrate
101
so as to define an active region surrounded by the field oxide films
102
. Further, an ion implantation of impurity into the active region was carried out to form a channel stopper. Subsequently, a thermal oxidation of silicon was carried out to form a gate oxide film
103
. A chemical vapor deposition method was carried out to form a polysilicon film having a thickness of 150 nanometers over an entire region of the substrate
101
. An n-type impurity such as phosphorus was doped into the deposited polysilicon film so as to reduce a resistivity of the polysilicon film. The impurity doped polysilicon film was then patterned by a photolithography to form a gate electrode
104
. A chemical vapor deposition was carried out to deposit a silicon oxide film on an entire region of the substrate
101
. The deposited silicon oxide film was then subjected to an anisotropic etching to form side wall oxide films
105
at opposite sides of the gate electrode
104
. An ion-implantation of arsenic into the substrate
101
wa
Lindsay Jr. Walter L.
NEC Corporation
Niebling John F.
Young & Thompson
LandOfFree
Method for forming a refractory metal silicide layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a refractory metal silicide layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a refractory metal silicide layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2500105