Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
1999-05-28
2001-03-06
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S233100, C327S291000, C327S299000
Reexamination Certificate
active
06198673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit such as SOG (Sea Of Gate), wherein unit cells with basic circuits formed therein are formed in a core area of a semiconductor chip in row and column form.
2. Description of the Related Art
In a conventional semiconductor integrated circuit such as SOG or the like, a high-driven driver is inserted between unit cells to control the time required to transfer a signal between the unit cells when a designer designs circuitry. However, no particular countermeasures were taken against its control on a hardware basis.
With miniaturization of semiconductor devices employed in a recent semiconductor integrated circuit devices, however, the proportion of a pass delay to signal increases from a delay time of a signal transmitted through a conventional semiconductor device, e.g., a transistor element itself to a delay time of a signal, which is developed between unit cells due to interconnections.
Therefore, there has been need to take countermeasures for adjusting the time required to transfer the signal between the unit cells.
SUMMARY OF THE INVENTION
With the foregoing in view, it is therefore an object of the present invention to provide a semiconductor integrated circuit capable of adjusting the time required to transfer a signal between unit cells.
For achieving the above object, a semiconductor integrated circuit having a core region and an I/O region according to the present invention comprises, a clock signal line for transferring a clock signal, basic unit cells and pull-up unit cells. The basic unit cells are arranged in rows and columns within the core region. Each of the basic unit cells has a PMOS active region and an NMOS active region. The pull-up unit cells are arranged in predetermined intervals between the basic unit cells. The pull-up unit cells are coupled to the signal line for pulling up an electric level of the clock signal line in response to the clock signal.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
REFERENCES:
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5771201 (1998-06-01), Cho
patent: 5854567 (1998-12-01), Meier et al.
Jones Volentine, L.L.C.
Mai Son
Oki Electric Industry Co., Ltd
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