Method of making dual damascene conductive interconnections...

Details Method of making dual damascene conductive interconnections... Method of making dual damascene conductive interconnections...

1998-10-14

2001-05-08

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S637000, C438S638000, C438S666000, C438S668000, C438S672000, C438S738000

Reexamination Certificate

active

06228758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to semiconductor processing, and, more particularly, to the formation of multi-level conductive interconnects on integrated circuit devices.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
One particular technique used to form such conductive lines and plugs is known as a dual damascene technique. One variation of this technique involves the formation of a first layer of a dielectric material, formation of a relatively thin etch stop layer (for example comprised of silicon nitride) above the first dielectric layer, patterning of the etch stop layer to define openings corresponding to plugs to be formed in the first dielectric layer, and formation of a second dielectric layer above the etch stop layer. Thereafter, an etching process is used to define an opening in the second dielectric layer, and to remove portions of the first dielectric layer positioned under the openings previously formed in the etch stop layer. The openings in the first and second layers of dielectric material correspond to a yet to be formed metal plug and metal line, respectively. Thereafter, the openings in the first and second dielectric layers are filled with an appropriate metal or layers of metal.
The dual damascene technique is very labor-intensive in that it requires the formation of three process layers, the first and second dielectric layers as well as the etch stop layer. Additionally, the etch stop layer, which is typically comprised of a material having a relatively high dielectric constant, such as silicon nitride with a dielectric constant of approximately eight, tends to increase the capacitance between the adjacent metal lines. This increase in capacitance tends to reduce the speed at which electrical signals may travel along the metal line, which may cause a reduction in the operating speed of the integrated circuit device and increase the power consumption of the device (which tends to cause heat to build up in the entire device, e.g., a microprocessor).
The present invention is directed to a method and device for solving some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to an integrated circuit device having improved conductive interconnections and method for making same. The method comprises forming first and second layers comprised of first and second dielectric materials, the first and second dielectric materials being selectively etchable with respect to one another. The second layer is formed above the first layer and in a previously formed opening in the first dielectric layer. The method further comprises removing portions of the second layer to define an opening in the second layer and to remove said second dielectric material from the opening in the first layer. The method also comprises forming a conductive material in the first and second openings in the first and second layers, respectively.
The present invention is also directed to an integrated circuit device having a novel conductive interconnection structure. The device is comprised of a first layer of a dielectric material and a second layer of a dielectric material positioned adjacent the first layer of dielectric material. The first and second layers of dielectric material have first and second openings formed therein, respectively. The device further comprises a conductive structure formed only in the first and second openings formed in the first and second layers of dielectric material.


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