Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-18
2001-08-21
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S256000, C438S399000, C438S637000
Reexamination Certificate
active
06277738
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method of reducing a contact resistance between a gate electrode(e.g. a word line in a semiconductor memory device) having a tungsten silicide film at the uppermost and another electrode (e.g. a bit line in a semiconductor memory device) to be formed in the later fabrication process.
In a cell area of semiconductor memory device, the active region(e.g. source/drain region) is coupled to the bit line though a contact hole, while in a peripheral circuit area a word line (or gate electrode) is coupled to the bit line through contact hole. The uppermost part of the word line (or gate electrode) is composed of tungsten silicide film and the bit line is generally composed of a doped polysilicon film(or conductive polysilicon film) or a polycide film. In the peripheral circuit area, a polysilicon bit line is coupled to the tungsten silicide (WSi
x
) word line.
When an interlayer insulating film is selectively etched so as to open contact holes, the surface of the tungsten silicide (WSi
x
) film is oxidized to generate a tungsten oxide (WO
3
) film thereon. Accordingly, in order to reduce the contact resistance with the bit line a washing process should be made, conventionally using HF or fluorine containing solution after the etch for contact hole formation. However, in the peripheral circuit area, the WO
3
film that has been formed during the dry etch of contact hole formation using CF
4
and O
2
gas is not effectively removed so that the contact resistance is undesirably high.
Also, a long-time washing using HF solution is required for completely removing the WO
3
film. However, The long-time washing causes problem in that the BPSG film(or the interlayer insulating film) is undesirably much etched, thereby undesirably enlarging the width of the contact hole. This problem occurs not only in the contact hole formation for exposing the surface of tungsten silicide film but also tungsten film.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing a contact resistance by effectively removing WO
3
film generated during an etch of contact hole formation.
Another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of reducing a contact resistance between a word line and a bit line.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device for effectively removing a WO
3
film generated on a tungsten silicide film without undesirable damage to an interlayer insulating film.
To achieve the objects of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a first electrode on a semiconductor substrate, said first electrode including a tungsten silicide(WSi
x
) layer at the uppermost part; forming an interlayer insulating film over the first electrode; selectively etching the interlayer insulating film to expose the tungsten silicide layer, wherein a tungsten oxide (WO
3
) film is generated on the tungsten silicide layer by the etching; washing the tungsten oxide film using an alkaline solution; and forming a second electrode coupled to the exposed tungsten silicide layer.
In one preferred embodiment, the alkaline solution is TMAH(tetra-methyl-ammonium-hydroxide) solution or TMAH containing solution and the TMAH solution is preferably about 2.35 wt % in density. Also, it is preferable that the washing step is performed at 60° C.~70° C. and the thickness of the WO
3
film removed in the step of washing is equal to or less than 50 Å. The interlayer insulating film may be composed of BPSG and the step of selectively etching the interlayer insulating film may be a dry etching by use of CF
4
+O
2
.
In another preferred embodiment, the method further comprises the step of performing an additive washing by use of HF or fluorine containing solution6 after the step of washing.
The present invention also provide a method of manufacturing a semiconductor memory device comprising the steps of: forming word lines on a semiconductor substrate that can be sectioned into a cell area and a peripheral circuit area, each of the word lines including a tungsten silicide layer at the uppermost part thereof; forming an interlayer insulating film over the word lines; selectively etching the interlayer insulating film so as to open contact holes some of which expose the semiconductor substrate in the cell area and another of which expose the word line in the peripheral circuit area, wherein tungsten oxide(WO
3
) films are generated on the tungsten silicide layer by the etching; and performing a washing process using alkaline solution to remove the tungsten oxide films.
In the preferred embodiments, the step of forming word lines comprises the steps of: forming a polysilicon film having 500 Å~900 Å in thickness; forming a WSi
x
film having 600 Å~900 Å in thickness; etching the WSi
x
film and the polysilicon film by photolithography to form gate electrodes; forming spacers on the sides of the gate electrodes. The interlayer insulating film may be composed of BPSG film having 700 Å~1100 Å in thickness and the step of etching the interlayer insulating film is made by dry etch by use of the mixed gas of CF
4
+O
2
. The alkaline solution used in the step of performing a washing process may be a 2.35 wt % of TMAH solution, 20 wt %~30 wt % of NH
4
OH containing solution, or a mixed chemical including at least H
2
O
2
solution. The step of performing a washing process may be preferably conducted at 50° C.~80° C. and more preferably at 60° C.~70° C. and still more preferably at about 65° C. Also, the method may further comprise the steps of forming a conductive polysilicon layer coupled to the tungsten silicide layer after the step of performing a washing process; and patterning the conductive polysilicon layer to form bit lines.
In addition, in the step of performing a washing process the etch condition may be preferably controlled such that the etch rate of the tungsten oxide film is 200 Å/min~400 Å/min and the etch rate of BPSG film is 60 Å/min~70 Å/min.
The method may further comprise the step of performing an additive washing by use of HF or fluorine containing solution after the step of washing.
The present invention still provides a method of forming contact holes in a semiconductor device, comprising the steps of:
opening contact holes by selectively etching an interlayer insulating film, wherein at least one of the contact holes exposes the surface of conductive tungsten containing film; and washing the inside of the contact holes using TMAH(tetra-methyl-ammonium-hydroxide) solution. This contact hole formation method may further comprise the step of performing an additive washing of the inside of the contact holes by use of HF or fluorine containing solution after the step of washing. The contact holes may be formed by dry etch using a mixed gas with CF
4
and O
2
and the conductive tungsten containing film can be a tungsten silicide film or a tungsten film.
In summary, according to the present invention washes, the WO
3
film generated during etching the BPSG interlayer insulating film for a contact hole formation is washed using an alkaline solution such as NH
4
OH solution or TMAH solution having high etch selectivity in order to reduce the contact resistance between a word line and bit line, in which the word line is composed of a tungsten silicide film at the uppermost part and the bit line is composed of conductive material such as doped polysilicon formed in later process.
REFERENCES:
patent: 5091763 (1992-02-01), Sanchez
patent: 5946595 (1999-08-01), Doan et al.
patent: 6136649 (2000-10-01), Hui et al.
patent: 57-107030 (1982-07-01), None
patent: 61-110462 (1986-05-01), None
patent: 63-265448 (1988-11-01), None
pat
Choi Hyung Bok
Kim Hyeon Soo
Park Chang Seo
Bowers Charles
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Nguyen Thanh
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