Semiconductor device of SOI structure with floating body region

Details Semiconductor device of SOI structure with floating body region Semiconductor device of SOI structure with floating body region

1999-09-24

2001-09-18

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C438S149000

Reexamination Certificate

active

06291857

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor device of SOI structure with a circuit configuration comprising a MOS transistor.
Description of the Background Art
FIG. 11
is a cross section illustrating the structure of a NMOS transistor having a conventional SOI structure. In the figure, the SOI structure comprises a semiconductor substrate
21
, a silicon oxide film
22
and a SOI layer
23
, and a NMOS transistor is formed in the SOI layer
23
.
Specifically, an N type source region
24
and an N type drain region
25
are selectively formed in the SOI layer
23
, the region between the source region
24
and the drain region
25
in the SOI layer
23
becomes a P type body region
26
, a gate oxide film
27
is formed on the surface of the body region
26
serving as a channel region, and a gate electrode
28
is formed on the gate oxide film
27
.
In the NMOS transistor of the SOI structure as described, when the body region
26
is brought into a floating state, the current driving ability is increased by parasitic bipolar operation. The reason for this is as follows.
Referring to
FIG. 11
, hole-electron pairs are generated by impact ionization. At this time, in the NMOS transistor, the electrons are extracted by the drain, and the holes are left in the body region
26
, thereby increasing the potential of the body region
26
. This causes a drop in the threshold voltage of the NMOS transistor having a threshold voltage characteristic as shown in
FIG. 12
, thereby increasing the current driving ability of the NMOS transistor.
The same is true for PMOS transistors. That is, when hole-electron pairs are generated by impact ionization in a PMOS transistor, the holes are extracted by the drain, and the electrons are left in a body region, thereby decreasing the potential of the body region. This causes a drop in the absolute value of the threshold voltage of the PMOS transistor having a threshold voltage characteristic as shown in
FIG. 12
, thereby increasing the current driving ability of the PMOS transistor.
Thus the MOS transistor of SOI structure has the advantage that its current driving ability is increased by bringing the body region into a floating state.
The MOS transistor of SOI structure in which the body region is in a floating state is, however, susceptible to the influence of soft error. For example, if in the body region
26
of a MOS transistor, large numbers of hole-electron pairs are generated due to the incidence of &agr; rays into the body region
26
, large numbers of holes are to be stored in the body region
26
. The NMOS transistor with large numbers of holes stored has no problems in its On-state, but causes a leakage current in its Off state, resulting in an unstable current operation.
Consequently, both merits and demerits arise when the body region of the MOS transistor of SOI structure is brought into a floating state. The body region of the MOS transistor staying in a floating state causes the problem that a leakage current is caused in its Off-state.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a semiconductor device comprises: a MIS transistor for signal processing formed in a SOI layer of SOI structure, the MIS transistor having (i) a gate that receives a first input signal expressing first/second logic, (ii) a first terminal from which an output signal based on the first input signal is outputted, (iii) a second terminal turning on/off between the first terminal and itself in response to the first/second logic expressed by the first input signal, respectively, and (iv) a body region; and a body region potential shifting means changing a first operation of bringing the body region of the MIS transistor into a floating state, to a second operation of the body region potential shifting toward the second terminal potential, between a first transition in which the first input signal transits from the second logic to the first logic, and a second transition in which the first input signal transits from the first logic expressed by the first input signal in the first transition, to the second logic.
According to a second aspect, the semiconductor device of the first aspect is characterized in that the body region potential shifting means includes a delay means receiving a second input signal and delaying the second input signal to generate the first input signal; and a switching element switching the first operation to the second operation based on the transition of the second input signal.
According to a third aspect, the semiconductor device of the second aspect is characterized in that the switching element has a switching transistor. The switching transistor includes a first terminal connected to the body region of the MIS transistor for signal processing, a second terminal connected to the second terminal of the MIS transistor, and a control terminal receiving the second input signal.
According to a fourth aspect, the semiconductor device of the first aspect further comprises: another MIS transistor for signal processing formed in a SOI layer of SOI structure, the another MIS transistor having (i) a gate that receives the first input signal, (ii) a first terminal connected to the first terminal of the MIS transistor, (iii) a second terminal turning on/off between the first terminal and itself in response to the second/first logic expressed by the first input signal, and (iv) a body region; and another body region potential shifting means changing a first operation of bringing the body region of the another MIS transistor for signal processing into a floating state, to a second operation of the body region potential shifting toward the second terminal potential, between the second transition of the first input signal and the first transition in which the second logic expressed by the first input signal in the second transition transits to the first logic.
According to a fifth aspect, the semiconductor device of the third aspect is characterized in that the MIS transistor for signal processing and the switching transistor are of an identical conductivity type; and the delay means includes a single inverter receiving the second input signal to output the first input signal.
According to a sixth aspect, the semiconductor device of the third aspect is characterized in that the MIS transistor for signal processing and the switching transistor are of an identical conductivity type; and the delay means includes series-connected inverters, the number of which is odd and not less than three, the odd-inverters receiving the second input signal into the first step inverter to output the first input signal from the final step inverter.
In the semiconductor device of the first aspect, when a MIS transistor for signal processing is in On-state by the first transition of a first input signal, its body region is maintained in a floating state, which permits current driving ability to be increased by parasitic bipolar effect. On the other hand, before the MIS transistor transits to Off-state by the second transition of the first input signal, the body region potential shifts toward the second terminal potential, thereby avoiding a leakage current.
In the semiconductor device of the second aspect, since a first input signal is obtained by delaying a second input signal, the transition of the first input signal is generated with a delay time, based on the transition of a second input signal. Thereby, before a MIS transistor for signal processing transits to Off-state, the body potential shifts toward the second terminal potential by switching a first operation to a second operation based on the transition of the second input signal.
In the semiconductor device of the third aspect, the second terminal of a MIS transistor for signal processing has the same potential as its body region, which permits the body region potential shifting toward the second terminal potential.
In the semiconductor device of the fourth aspect, when another MIS transistor for signal processing is in On-stat

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