Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-08
2001-05-29
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S327000, C257S328000, C257S329000, C257S330000, C257S332000, C438S201000, C438S211000, C438S212000, C438S259000, C438S268000, C438S270000, C438S271000, C438S587000, C438S588000, C438S589000
Reexamination Certificate
active
06239465
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more particularly, to a MOS-type semiconductor memory device which allows electrical writing and erasing, and a fabrication method therefor.
2. Description of the Related Air
FIG. 15
shows a cross-sectional structure of a memory cell in a conventional NOR-type flash memory. In
FIG. 15
, there are shown a p-type silicon semiconductor substrate
1
, a field oxide film
2
having a thickness of about 400 nm to 800 nm, an oxide film
3
about 10 nm thick formed by thermally oxidizing the silicon semiconductor substrate, serving as a first gate insulating film of the non-volatile memory, a floating gate
4
made from a first polycrystalline silicon film, a second gate insulating film
5
about 20 nm thick, a control gate
6
made from a second polycrystalline silicon film, an impurity diffusion layer
7
having a conductivity type opposite to that of the substrate used for making a source diffusion layer have a high breakdown voltage, an n
+
diffusion layer for the source
8
, an n
+
diffusion layer for the drain
9
, a side-wall insulating film
10
for a gate electrode, an interlayer insulating film
11
, a metal-wiring lead-out electrode
12
for the source, a metal-wiring lead-out electrode
13
for the drain, and a metal-wiring lead-out electrode
14
for the control gate. In a writing operation of the non-volatile semiconductor memory device having such a structure, a voltage is applied between the control-gate electrode
14
and the drain electrode
13
to generate an avalanche hot electron between the drain
9
and the substrate
1
, and the electron is injected into the floating gate
4
. In an erasing operation, a voltage is applied between the control-gate electrode
14
and the source electrode
12
, and the electron is drawn from the floating gate
4
to the source
8
by Fowler-Nordheim tunneling (or F-N tunneling) current.
As scaling-down of an MOS transistor is further progressed to increase an integration scale of the MOS memory devices, the conventional memory cell will have no choice but encounter the following drawbacks:
(1) Since it is said that the lowest limit of a thin-film for a tunneling oxide film is about 8 nm thick in a memory cell using an F-N tunneling current, a scaling rule (a proportional reduction rule between a device dimension and a voltage to be applied, in scaling down) is not satisfied for a thin film having a film thickness less than that.
(2) When an effective channel length is made smaller by scaling-down, it is difficult to control a punch-through breakdown voltage and a leakage current.
(3) As capacitance of a capacitor coupled with the floating gate is reduced, erasing and writing characteristics deteriorate. These three drawbacks will be described below in detail.
FIG. 1
shows a capacitor model in a floating-type semiconductor memory cell. With this model, floating gate voltages Vfg(W) for writing and Vfg(E) for erasing can be expressed, respectively, as follows:
Writing
Vfg(W)=(C
2
·Vcg+C
3
·Vd)/(C
1
+C
2
+C
3
+C
4
) (1)
Erasing
Vfg(E)=(C
2
·Vcg+C
4
·Vs)/(C
1
+C
2
+C
3
+C
4
) (2)
where, C
1
, C
2
, C
3
, and C
4
indicate the capacitance of capacitors formed between the floating gate
4
and the substrate
1
, the control gate
6
and the floating gate
4
, the floating gate
4
and the diffusion-layer drain
9
, and the floating gate
4
and the diffusion-layer source
8
, respectively, and Vcg, Vs, and Vd indicate the control gate voltage, the source voltage, and the drain voltage, respectively.
In general, to increase writing efficiency, since Vcg and Vd are both positive values, it is desirable that the capacitance of the capacitors C
2
and C
3
are made as large as possible in expression (1). Then, the effective voltage Vfg(W) applied to the floating gate increases and the injection efficiency of the avalanche hot electron into the floating gate, namely, writing efficiency, is improved. As a result, a writing time becomes short.
On the other hand, during erasing, since Vcg is zero or a negative value and Vs is a positive value, capacitance relationship of C
2
>>C
4
is the most appropriate condition in expression (2). When this condition is satisfied, the effective voltage Vfg(E) applied to the floating gate increases. Therefore, the drawing efficiency of the electron from the floating gate to the source by the use of the F-N tunneling current, namely, erasing efficiency, is improved. As a result, an erasing period becomes short.
From the above reasons, when a device is scaled down finer only according to the scaling rule without changing the shape of MOS transistors, a range of choice in capacitance becomes narrower. Therefore, a non-volatile semiconductor memory device free from the above drawbacks in scaling-down has been demanded.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a non-volatile semiconductor memory device which allows the writing and erasing times to be reduced without lowering stability of the device characteristics due to the transistor scaling rule in highly integrated memory devices.
In a non-volatile semiconductor memory device according to the present invention, the inside wall surface of a trench formed in the depth direction of the semiconductor substrate serves as a device region in which the diffusion layers for source and drain, the floating-gate electrode, and the control-gate electrode are disposed so as to form a channel area in the depth direction. In addition, the trench is formed such that the peripheral width of the aperture of a vertical trench is made larger at the drain area in the upper portion than that at the source area in the lower portion.
According to the present invention, each of the memory cells is separated in the first direction on a plane of the semiconductor substrate surface by insulating walls (parallel to each other) extending in a second direction crossing the first direction on the same plane and extending in depth direction from an upper surface of the drain region to at least the lower surface of the source region, wherein the source diffusion layer is continuously extended over a series of the memory cells arranged in the second direction between each neighboring pair of the parallel insulating walls.
According to the present invention, the trench for the device region is formed such that the first trench having an aperture is formed on a semiconductor surface shallower than a source diffusion layer while the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.
According to the present invention, the trench for the device region is formed such that the inside wall of the first trench is concave while the inside walls of the second trench are essentially perpendicular to the plane of the semiconductor substrate surface.
REFERENCES:
patent: 6093606 (2000-07-01), Liu et al.
patent: 6147378 (2000-11-01), Liu et al.
Armstrong Westerman Hattori McLeland & Naughton LLP
Flynn Nathan
Fujitsu Ltd.
Quinto Kevin
LandOfFree
Non-volatile semiconductor memory device having vertical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory device having vertical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device having vertical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2499128