Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1996-09-04
2001-08-07
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000
Reexamination Certificate
active
06272646
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to programmable logic devices (PLDS) and, more particularly to programmable logic devices having an integrated phase lock loop to provide enhanced clocking capabilities and other additional features.
BACKGROUND OF THE INVENTION
Modern computers require various clocks operating at different frequencies to operate different individual components of individual on-board devices. In a programmable logic device (PLD), to realize various clock frequencies at the particular macro cells (or registers) of the device, previous approaches have traced multiple clock signals throughout the layout of the chip to supply the particular cells with the desired frequencies.
Modern semiconductor manufacturers typically specialize in specific component manufacturing processes in which they have expertise. For example, a manufacturer skilled in the fabrication of programmable logic devices may not necessarily be skilled in the manufacturing of phase locked loop (PLL) devices.
Personal Computer (PC) motherboard applications need a standard set of frequencies to operate. These frequencies are typically generated from a reference clock frequency. Since many designs use multiples of certain input frequencies, design engineers typically u se delay loops or counters on a PLD to achieve the various frequencies. Consequentially, the logic resources available in the programmable logic device are expended to implement this remedial frequency adjustment. As a result, either less programmable features may be implemented, or either more costly PLD complex programmable devices (CPLDs) must be implemented or field programmable gate arrays (FPGAs).
Another problem occurs when industry standards change. When standards change, design engineers typically must redesign their entire chips. For example, the peripheral connect interface (PCI) bus currently uses a bus speed of
33
MHz. It is anticipated that the industry standard for the PCI bus will be increased to 66 MHz in the future. The use of previous approaches (such as delay loops in the programming elements of the logic device) would require a significant amount of design work to upgrade to 66 MHz or any other new standard. By reducing setup times, a performance improvement may be realized.
SUMMARY OF THE INVENTION
The present invention integrates a phase lock loop (PLL) with a programmable logic device (PLD) to realize a flexible PLD with a variety of clocking options. The present invention generates multiple clock frequencies internally to a programmable logic device using a single reference clock input. The programmer can dynamically change the functionality of the programmable logic device. As a result, a “virtual hardware device” is realized. The ability to change the frequency of operation also dynamically offers a tremendous advantage to users of reconfigurable computing.
Objects, features and advantages of the present invention include providing a dynamically programmable multiple frequency clock generator with a programmable logic device which will create a device more efficient than either of the two devices considered separately. The present invention will provide a wide output frequency range that can be dynamically adjusted, a number of individually programmable outputs, a high degree of control of output skew, an internal loop filtering which would not require external components and a wide number of output frequencies. The present invention may be configured to feed a clock distribution network of targeted programmable logic devices and may be accessible to one or more input/output (I/O) pins. In a particular embodiment, the present invention may provide a low clock jitter (less than 200 ps), a variable duty cycle (ranging between 40% and 60%), either a 3.3 volt or 5.0 volt input supply voltage operation range, a matched output impedance and a low power consumption. The present invention may be implemented using high speed CMOS implementation.
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Cypress Data Book 1996—“Programmable Logic”, pp. 2-1 to 2-5, pp. 3-1, pp. 3-8 to 3-14, San Jose CA.
Rangasayee Krishna
Shannon John
Butler Dennis M.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
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