Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-16
2001-01-16
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06175136
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a CMOS device with an improved lightly doped drain structure suppressing hot carriers, which allows the CMOS device to exhibit high performance and to be scaled down, as well as a method of forming the same.
As the MOS field effect transistor has been scaled down, serious problems are raised with deterioration of performance of the MOS field effect transistor due to hot carrier injection and also with leakage of current between a source and a drain of the MOS field effect transistor due to short channel effects.
In order to avoid the deterioration of the performance due to the hot carrier injections, it is effective to relax the electric field in the vicinity of the drain of the MOS field effect transistor. In order to relax the electric field, it is effective to form a lightly doped drain structure of the MOS field effect transistor.
On the other hand, the leakage of current between the source and drain of the MOS field effect transistor is caused by punch through phenomenons. The punch through phenomenons are caused by the fact that the space charge regions of the source and drain regions are made adjacent to each other.
The MOS field effect transistors usually have a double-layered structure like a gate electrode that comprises an n-type polysilicon layer or a double layered structure of an n-type polysilicon layer and a metal suicide layer. In this case, an n-channel MOS field effect transistor is a surface channel MOS field effect transistor, whilst a p-channel MOS field effect transistor is a buried channel MOS field effect transistor. A remarkable leakage of current between source and drain regions due to the punch through phenomenon may appear in the buried p-channel MOS field effect transistor. However, the buried p-channel MOS field effect transistor has a sufficient distance between a channel region and a gate oxide film for preventing hot carriers from being injected into the gate oxide film, for which reason the buried p-channel MOS field effect transistor reduces the deterioration of the performance due to the hot carrier injection into the oxide film.
In order to settle the above problem with the source-drain current leakage due to the punch through phenomenon, it is effective to form punch through stopper regions under the lightly doped drain p-type diffusion layers of the p-channel MOS field effect transistor. The following descriptions will focus on the p-channel MOS field effect transistor with the punch through stopper regions under the lightly doped drain p-type diffusion layers.
FIG. 1
is a fragmentary cross sectional elevation view illustrative of a conventional CMOS device including a p-channel MOS field effect transistor with punch through stopper regions. The CMOS device is formed on a p-channel semiconductor substrate
10
. Field oxide films
20
having a thickness of about 300-500 nanometers are selectively formed over a surface of the p-channel semiconductor substrate
10
to define active regions of the p-channel semiconductor substrate
10
. Further, a p-type impurity such as boron is selectively ion-implanted into regions under the field oxide films
20
thereby forming p-type channel stoppers
21
. A p-well region
11
and an n-well region
12
are formed in an upper region of the p-channel semiconductor substrate
10
. The p-well region
11
is selectively formed by a selective ion-implantation of a p-type impurity such as boron into the p-channel semiconductor substrate
10
and a subsequent heat treatment at a temperature of 1000-1200° C. in a nitrogen atmosphere for 30-60 minutes. On the other hand, the n-well region
12
is selectively formed by a selective ion-implantation of an n-type impurity such as phosphorus or arsenic into the p-channel semiconductor substrate
10
and the above subsequent heat treatment.
A gate oxide film
30
having a thickness of about 6-10 nanometers is formed which extends over the p-well region
11
and the n-well region
12
as well as over the field oxide films
20
. A heavily doped n+-type polysilicon layer
32
is entirely formed which extends over the gate oxide film
30
. Further, a metal silicide layer
33
such as a tungsten silicide layer is formed which extends over the heavily doped n+-type polysilicon layer
32
. The laminations of the heavily doped n+-type polysilicon layer
32
and the metal silicide layer
33
are patterned by a photo-lithography technique to thereby form gate electrodes
31
which comprise the laminations of the heavily doped n+-type polysilicon layer
32
and the metal silicide layer
33
. An n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the p-well region
11
by use of the gate electrode
31
and the field oxide films
20
as masks whereby lightly doped drain n−-type diffusion layers
41
are formed in the p-well region
11
. A p-type impurity such as boron or boron fluoride is also selectively ion-implanted into the n-well region
12
by use of the gate electrode
31
and the field oxide films
20
as masks whereby lightly doped drain p−-type diffusion layers
42
are formed in the n-well region
12
. Further, an n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the n-well region
12
and under the lightly doped drain p−-type diffusion layers
42
but only in the vicinity of a channel region defined between the lightly doped drain p−-type diffusion layers
42
whereby punch through stopper regions
43
are selectively formed in the n-well region
12
and under the lightly doped drain p−-type diffusion layers
42
but only in the vicinity of a channel region defined between the lightly doped drain p−-type diffusion layers
42
.
A silicon oxide film is entirely formed which extends over the gate electrodes
31
, the lightly doped drain n−-type diffusion layers
41
, and the lightly doped drain p−-type diffusion layers
42
as well as the field oxide films
20
. The silicon oxide film is then subjected to an etch back to selectively form side wall oxide films
50
on side walls of the gate electrodes
31
.
An n-type impurity such as phosphorus and arsenic is selectively ion-implanted into the p-well region
11
by use of the field oxide films
20
, the gate electrode
31
and the side wall oxide films
50
as masks to selectively form source/drain n+-type diffusion layers
61
in the p-well region
11
. A p-type impurity such as boron is selectively ion-implanted into the n-well region
12
by use of the field oxide films
20
, the gate electrode
31
and the side wall oxide films
50
as masks to selectively form source/drain p+-type diffusion layers
62
in the p-well region
12
. As a result, an n-channel MOS field effect transistor is formed in the p-well region
11
, whilst a p-channel MOS field effect transistor is formed in the n-well region
12
.
As described above, the conventional CMOS device has the punch through stoppers
43
in the n-well region
12
and under the side wall oxide films
50
in order to prevent the punch through of the p-channel MOS field effect transistor or prevent leakage of current between the source and drain regions of the p-channel MOS field effect transistor.
Since, however, boron as the p-type impurity has a large diffusion constant in silicon, the p-type diffusion layers such as the lightly doped drain layers
42
and the source and drain diffusion layers
62
show large diffusion in a lateral direction. For this reason, it is required to provide a large width of the side walls so as to prevent the n-type diffusion layers that serve as the punch through stoppers from being captured by or overlapped by the p-type diffusion layers whereby the punch through stoppers can no longer exhibit those function for preventing the punch through between the source and drain.
The side walls of the n-channel and p-channel MOS field effect transistors selectively formed in the p-well and n-well regions
11
Fourson George
NEC Corporation
Young & Thompson
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