Method of planarizing inter-metal dielectric layer

Details Method of planarizing inter-metal dielectric layer Method of planarizing inter-metal dielectric layer

1999-06-18

2001-08-21

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S637000, C438S673000, C438S627000, C438S643000, C438S653000

Reexamination Certificate

active

06277732

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 8108611, filed May 26, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of planarizing an inter-metal dielectric layer of a semiconductor device. More particularly, the present invention relates to a method of forming a planarized inter-metal dielectric layer that has a low dielectric constant (low k).
2. Description of Related Art
Recently, semiconductor manufacturing has advanced into the deep submicron process. Beside the miniaturization of semiconductor transistors so that operating speed of each device is increased, the deployment of innovative materials further boosts the performance and reliability of the devices.
In general, when the distance between neighboring metal lines in a semiconductor circuit is reduced, transmission of electrical signals through the metal lines is delayed. A phenomenon known as resistance-capacitance time delay (or RC time delay) is one of the factors that limit the operating speed of a device.
To reduce the RC time delay, a low resistance material is used to form the metal lines and low dielectric constant material is used to form the inter-metal dielectric layer.
However, low dielectric constant material typically comprises organic polymer. Thermal conductivity of the organic polymer is usually low. Thus, when the inter-metal dielectric layer is formed using the organic polymer, a reliability problem of metal lines may arise.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a process for planarizing an inter-metal dielectric layer. Both low dielectric constant organic material and low dielectric constant inorganic material are used to form the inter-metal dielectric layer. Hence, severity of the thermal conductivity problem resulting from the use of organic material in conventional method can be minimized.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a process for planarizing an inter-metal dielectric layer. A substrate having a plurality of metal lines thereon is provided. Some metal lines are formed close to each other, resulting in densely packed metal line regions. In contrast, some of the metal lines are laid further apart, resulting in loosely packed metal line regions. A dielectric liner layer is formed covering the metal lines and the exposed substrate. A nitridation treatment of the dielectric liner layer is carried out. Organic dielectric layer having a low dielectric constant is deposited over the dielectric liner layer so that the densely packed metal line regions are completely filled while the loosely packed metal line region is only partially filled. Using the dielectric liner layer as an etching stop layer, the organic dielectric layer is etched by performing a reactive ion etching operation. Inorganic dielectric layer having a low dielectric constant is deposited over the organic dielectric layer. The inorganic dielectric layer has a thickness greater than the height of the metal lines. A cap dielectric layer is formed over the inorganic dielectric layer, and the cap dielectric layer is planarized by performing a chemical-mechanical polishing operation. A via is formed through the cap dielectric layer, the inorganic dielectric layer, the organic dielectric layer and the dielectric liner layer such that a top surface of the metal line is exposed. An electron beam curing operation is carried out so that the organic dielectric layer on the sidewall of the via is more dense. Lastly, a barrier layer and a metal plug are sequentially formed inside the via.
In this invention, low k organic dielectric layer is used to completely fill the gaps in the densely packed metal line regions, but the gaps in the loosely packed metal line regions are only partially filled. A low k inorganic dielectric layer having a higher thermal conductivity is deposited over the organic dielectric layer next. The inorganic dielectric layer also fills the remaining space in the loosely packed metal line regions not yet covered by the organic dielectric layer.
By filling the gaps in the densely packed metal line regions with low k organic dielectric layer, the dielectric constant of the inter-metal dielectric layer between two adjacent metal lines is lowered. Therefore, the speed of transmission of electrical signals through the metal lines is increased.
By forming a low k organic dielectric layer followed by forming a low k inorganic dielectric layer having a higher thermal conductivity, the metal line regions have a lower overall dielectric constant. Moreover, the higher thermal conductivity of the inorganic dielectric layer also makes the cooling of metal line regions much faster.
In addition, when the dielectric liner layer is formed by chemical vapor deposition, the ratio between oxygen and tetra-ethyl-ortho-silicate (TEOS) gas sources can be suitably adjusted so that a thicker liner layer is formed on the top surface of the metal lines while a thinner liner layer is formed on the sidewalls of the metal lines. The thicker top liner layer is much better at protecting the metal line surface while the thinner sidewall liner layer lowers the dielectric constant of the inter-metal line dielectric layer between two adjacent metal lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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