Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1999-01-27
2001-09-18
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S228000, C712S248000, C712S217000, C711S169000, C711S149000, C711S144000, C711S123000, C711S126000, C710S033000, C709S241000
Reexamination Certificate
active
06292888
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the area of digital processors of all sizes and sorts, and pertains more particularly to apparatus and methods for loading and storing of information to and from registers files for such processors.
BACKGROUND OF THE INVENTION
An electronic processor, such as a microprocessor used in a personal computer or network device, contains registers that hold values upon which the processor's instructions act directly. To perform a simple integer addition instruction, for example, integers are loaded into each of two registers. The addition instruction operates upon the integers in the two registers and stores the resulting sum in a third register. Typically, the resulting sum is then saved in a memory location by another instruction. The three registers are then free to be used for a following instruction.
Typical processors have several registers. In some designs in the art, the registers are designed for general-purpose use. In others, particular registers are designed for specific purposes, such as to accumulate the results of calculations or to hold pointers to memory addresses. The collection of all such registers is known in the art as a register file.
When one program or program thread finishes executing and another begins, or an interrupt service routine is invoked, a context change must take place. This change is known in the art as a context switch. When a context switch takes place, the last values in the registers may have to be saved for later use. Once such values are saved, the context of the new thread must be loaded. The context consists at least of the address in memory of the first instruction of the thread, which is loaded into a program counter, and the initial values of registers. After the context switch, the first instruction of the new thread, as indicated by the program counter, is fetched and executed, operating upon the new initial register values.
For the purposes of the present disclosure it is important that some distinctions be made in parts of a processor. Depending on the nature of a processor for example, there may be relatively few distinct parts, or there may be a larger number of parts. Some processors are highly dedicated to a single function (embedded microcontrollers for example), and others have multiple functions, having such as fetch units, load/store units, and multiple functional units for executing instructions, such as integer units, floating point units, and branch prediction units. Also, the terminology in the art is loosely applied as to what precisely is a processor, a CPU, a microprocessor, and so on.
Regardless of the loosely applied terminology in the art and imprecise definitions, a clear distinction can be made for the purpose of the present descriptions. A distinct part of a processor of any sort executes instructions from an instruction stream. Other parts of a processor do not. For the purpose of the present description the part of any processor that executes instructions will be termed the instruction processor (IP).
In conventional processors in the prior art, a context switch is performed by a sequence of instructions executed by the IP, like any other program. Store instructions are executed by the IP to save register values to main memory or cache, and load instructions are used by the IP to fetch new register values from main memory or cache. Since there are typically several register values to be stored and several more to be loaded, a number of instructions are typically required, using a relatively long period of time in IP cycles. In processors with instructions that load and store blocks of memory, the process can be accelerated, but significant IP overhead is still involved.
Instructions that load and store from memory or cache typically take longer to execute than instructions that operate directly on register contents, so the time required for a context switch is even longer. For these two reasons, a context switch consumes a relatively large number of IP cycles. While the IP is occupied with a context switch, no useful calculations associated with the old or the new thread are executed. The context switch is thus pure overhead. Because context switching is a critical operation that must be completed before any other thread can run, no programs can be allowed to interrupt the context switch.
Having the IP completely unavailable for an extended period has been a major obstacle in system design. For example, it can interfere with the timely servicing of interrupts or the response to real time inputs.
In many systems context switching occurs so frequently that a relatively large proportion of processing capability is wasted. For example, in a personal computer where interrupts are used to service I/O devices, a context switch may occur each time an interrupt service routine is invoked. The burden of context switching is particularly high in real time systems that are required to respond quickly to many inputs. The bottleneck of context switching has remained a long-standing problem in processor design that has not been adequately addressed in the prior art.
The present invention represents a solution to this long-standing problem, at a cost of very little added logic in the system design. In the present invention a new register transfer unit loads and stores register values independently of the IP and in parallel with the processing of normal instructions. No load and store instructions are executed by the IP for data transfer to and from register files.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention an electronic processing system is provided, comprising at least two register files; an instruction processor coupled to the at least two register files for processing instructions using data in the register files; a data repository; and a register transfer unit coupled to the at least two register files and the data repository. Both the instruction processor and the register transfer unit are enabled to alter the states for the register files, and wherein the instruction processor and the register transfer unit take control of a register file only according to specific states of the register files.
In this embodiment a register file is never under control simultaneously of the register transfer unit and the instruction processor. Also in this embodiment register files exist in any one of five states, a first state indicating a file is in use by the instruction processor, a second state indicating the register file is released by the instruction processor with valid data to be stored, a third state indicating the register file is under control of the register transfer unit, a fourth state indicating the register file has no valid data and is available, and a fifth state indicating the register file is loaded with valid data and is ready for processing by the instruction processor. Typically a register file passes from state
1
, to state
2
, to state
3
wherein the register transfer unit unloads valid data from the register file, to state
4
, back to state
3
wherein the register transfer unit loads new valid data to the register file, to state
5
, and back again to state
1
.
In some cases a register file may pass from state
1
, directly to state
4
, to state
3
wherein the register transfer unit loads new data, to state
5
, and back again to state
1
. Status may in some cases be maintained for data as well as for register files, and the register transfer unit may then take control of a register file according to both a register file state and a data state.
In some embodiments the instruction processor, the first and second register files, and the register transfer unit are all implemented as semiconductor elements on a single chip. In other the instruction processor, the first and second register files, the register transfer unit, and the data repository are all implemented as semiconductor elements on a single chip.
In some preferred embodiments the processing system is a multi-streaming system having plural hardware stre
Nemirovsky Adolfo M.
Nemirovsky Mario D.
Sankar Narendra
Boys Donald R.
Central Coast Patent Agency Inc.
Clearwater Networks, Inc.
Pan Daniel H.
LandOfFree
Register transfer unit for electronic processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Register transfer unit for electronic processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Register transfer unit for electronic processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2496946