Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-08
2001-03-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S403000, C257S406000, C257S500000
Reexamination Certificate
active
06198140
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of Japanese Patent Applications No. 10-270537 filed on Sep. 8, 1998, No. 11-216301 filed on Jul. 30, 1999, and No. 11-216323 filed on Jul. 30, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device including several MOS transistors and a method of manufacturing the semiconductor device.
2. Description of the Related Arts
A fine structure is indispensable for a logical circuit transistor to improve an operating speed and to reduce its cost. Further, there is a tendency that a power supply voltage is decreased to decrease a consumption power. On the other hand, another type of transistor subjected to input and output voltages, i.e., the voltage applied across a source and a drain and the voltage applied to a gate, which are higher than those for the general logical circuit, is required for a sensor, an input-output interface of a power supply, for writing or erasing information in a nonvolatile memory such as a flash-memory, or the like. In this kind of transistor, characteristics such as a life of a gate oxide film, resistance with respect to hot carriers, and resistances of pn junction withstand voltage and isolation withstand voltage between elements are important rather than the operating speed.
When several kinds of transistors necessitating different operating voltages are mounted on a silicon substrate, conventionally, using a structure of one of the transistors as a basis, structures of the other kinds of transistors are determined. Usually, a standard transistor for a logical circuit, which is subjected to a low operating voltage and has a fine structure as described above, is selected as the basic transistor structure. Then, the other structures of the transistors necessitating high operating voltages are determined while securing transistor fine structures and considering the resistances described above. When this semiconductor device is manufactured, sources, drains, and the like are formed separately for the respective transistors based on the kinds of the transistors.
JP No. 2644776 discloses a method (first conventional example) for manufacturing a semiconductor device including a high-voltage transistor and a low-voltage transistor. In the method, when impurities are implanted into a lower side of an element isolation oxide film of a silicon wafer to form a channel stopper layer, an implantation amount of impurities is controlled so that it becomes small at the high-voltage transistor side. Accordingly, impurities are suppressed from being diffused into an element region, resulting in an improved pn junction withstand voltage of the high-voltage transistor.
JP-A-9-139382 proposes a method (second conventional example) for manufacturing a semiconductor device having a memory cell isolated by an element isolation oxide film with a narrow width, and a high withstand voltage transistor isolated by an element isolation oxide film with a wide width to form a peripheral circuit. That is, the semiconductor device has two element isolation oxide films having different thicknesses. In the method, two impurity implantation steps are performed for forming a channel stopper layer. One of the steps is shallow impurity implantation which is carried out so that impurities reach the bottom of the thin element isolation oxide film. The other of the steps is a deep impurity implantation which is carried out so that impurities reach the bottom of the thick element isolation oxide film.
Also, JP-A-8-111461 proposes a method (third conventional example) for manufacturing a semiconductor device having first and second transistor regions. In the method, a low-concentration impurity region as an electric field relaxation layer is formed to extend under a spacer in the first transistor region by obliquely rotating implantation or the like, while no low-concentration impurity region is formed in the second transistor region. Accordingly, the first transistor region can have a threshold voltage higher than that of the second transistor region without increasing a number of photo-lithography steps.
In a method (fourth conventional example) disclosed in JP-A-8-293598, an impurity implantation step for controlling threshold voltages of transistors is performed twice utilizing photo-lithography technique as first and second steps. The first step is for implanting impurities at a low impurity concentration into a first region of a region where a channel is to be formed in a silicon wafer. The second step is for implanting impurities at a high impurity concentration into a second region of the region. In a transistor region with a high threshold voltage, the area of the second region is increased, while in a transistor region with a low threshold voltage, the area of the first region is increased. Accordingly, even when more than two kinds of threshold voltages are required, it is sufficient to perform the first and second steps.
However, in the first and second conventional examples, it is necessary to perform ion implantation several times in accordance with the kinds of the transistors. The third and fourth conventional examples propose the methods which do not complicate the manufacturing process. However, the third conventional example has no flexibility because it produces only a slight difference between the two threshold voltages of the transistors. In the fourth conventional example, an unnecessary impurity layer is formed, and therefore, it is not always suitable for the impurity layers of the transistors.
Thus, in the conventional semiconductor device in which the impurity layers are arranged in the respective transistors necessitating different withstand voltages and the threshold voltages, profiles of impurity concentrations in the semiconductor substrate are complicated and the number of the manufacturing processes is increased. Further, in this case, because heat histories are complicated to make it difficult to provide desirable profiles. As a result, the characteristics of the transistors easily have large variations, and the wafer process cannot be rapidly performed with a high yield.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem. An object of the present invention is to provide a semiconductor device which is manufactured by a wafer process speedily performed at a high yield while securing sufficient transistor resistances. Another object of the present invention is to provide a method of manufacturing the same.
A semiconductor device according to the present invention has first and second transistors, and a first operating voltage for operating the first transistor is larger than a second operating voltage for operating the second transistor. In the semiconductor device, a gate length of a first gate portion of the first transistor is longer than that of a second gate portion of the second transistor. A thickness of a first gate insulating film of the first transistor is thicker than that of a second gate insulating film of the second transistor. A well has an impurity concentration profile identical for the first and second transistors. Further, an impurity amount implanted into a surface portion of a first transistor region for controlling a threshold voltage of the first transistor is equal to that for controlling the second transistor. Otherwise, the first source and the first drain of the first transistor have impurity concentration profiles approximately identical with the second source and the second drain of the second transistor.
Thus, the larger the operating voltage of the transistor is, the longer the gate length is, and the thicker the thickness of the gate insulating film is. Accordingly, electric fields produced at a channel and the gate insulating film in the first transistor having a higher operating voltage are relaxed to improve resistances of the transistor. In the second transistor having a lower operating v
Isobe Yoshihiko
Muramoto Hidetoshi
Chaudhuri Olik
Denso Corporation
Pham Hoai
Pillsbury & Winthrop LLP
LandOfFree
Semiconductor device including several transistors and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including several transistors and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including several transistors and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2496901