Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-09-26
2001-08-28
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C714S037000, C714S039000, C714S045000, C714S048000, C714S025000, C714S724000, C714S726000, C714S732000, C714S733000
Reexamination Certificate
active
06282134
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a memory test method and to a nonvolatile memory with low error masking probability. In particular, the invention relates to flash memories.
BACKGROUND OF THE INVENTION
As known, memory test methods are intended to cover and screen various types of possible defects present in memories, so as to ensure reliability of the end product. Memory tests are carried out at different manufacturing stages of the memory using special equipment, exploiting special internally implemented test modes. Memory tests are typically performed at Wafer Sort Level, Final Test Level and Final Device Characterization Level.
Specifically, the Wafer Sort Level test is carried out by connecting one or more memories belonging to a same wafer to a test machine which generates the addresses and timing clocks fed to each tested memory in the wafer; then a test pattern is written in each tested memory; data are read from each memory and furnished to the test machine to be compared with expected readings, to detect any fault.
The wafer sort level testers are limited in the array scanning speed; in particular, most of the memory testers provide the facility of multiple strobes in a same cycle time (synchronous mode testing, e.g., burst mode testing), which allows to perform data check reading of more than one address location in a same cycle time. Indeed, presently burst mode testing works on the principle of outputting the data read from the matrix in a pipeline way. The matrix array is divided into two independent halves called even and odd matrices, each having a respective set of 16 sense amplifiers for reading. During the device testing, reading is commanded by the tester, which furnishes the beginning address for starting the burst, and a clock RD for synchronization. Then, the memory generates consecutive addresses synchronized with read requests fed to the device through the clock RD. The addresses are decoded separately for the two matrix parts and reading is controlled by even/odd priority signals generated by a timing control logic in the memory. The addresses are linearly incremented in synchronization with the external clock RD and sequence reading is continued until the tester initiates a new burst sequence by latching a new address into the memory through a pin ALE provided for the purpose.
To test the correct device functionality and screen any possible sensing marginalities, a large number of tests are performed at various stages of Wafer Sort Flow, each needing to scan the whole matrix at least once. Therefore the test time during production is huge. Furthermore the minimum obtainable cycle time at Wafer Sort Level is limited, in the best case, to 100 ns, which is much larger than the access time specification of present flash memories. Thus, testing cannot be made at the memory operative speed. On the other hand, some defects may be detected only at high speed cycling, because otherwise the possible noise conditions do not intervene or get unnoticed.
To reduce the test time, the read data are often compressed internally to the device and the compression result, defining a code and also called “signature”, is fed to the test machine and compared to an expected result. Thus, the tester does not need to receive all read data, but only a final code (the signature) that is uniquely evaluated as a function of the read data and the sequence in which it occurs; thereby the signatures obtained after a partial or a complete matrix scan flag the possible errors occurred during scanning.
According to a widespread solution, used in particular for ROMs and called checksum method, the memory array is internally read in a random manner using LFSRs (Linear Feedback Shift Registers) for generating random addresses; at each scan, the read data are summed in a binary way to the previous result; so, if a ROM to be checked consists of 2
N
data words and each data word contains B bits, the checksum is formed by the modulo-2
k
arithmetic sum of the 2
N
data words in the ROM, where k is arbitrary. This means that all words in ROM are added together and k least significant terms of the sum form the signature or checksum. The result (signature) is fed at preset intervals or at the end of matrix scan to the tester to be compared for finding any failures.
Another popular solution particularly used for SRAM/DRAMs uses the LFSRs to generate random addresses and data pattern. The internal verification consists of two steps for every randomly addressed location. In the first step, the random data is written at the random address generated. The second step confirms the data back by reading. In some other approaches the data read are compressed in a response analyzer. The compression algorithm is fixed for the entire duration of the matrix scan. Thereby, at any time, the signature Q(t) present in the compressor unit may be mathematically expressed by:
Q(t)=f(data, Q(t−1)) (1)
wherein data is the just read data and Q(t−1) is the previous signature code.
A block diagram of a known memory device showing known elements as regards testing is shown in FIG.
1
. The memory device
1
comprises an address counter
2
receiving from the tester an initial address A
0
and a synchronization signal RD and generating a sequence of reading addresses A; a matrix
3
receiving from the address counter
2
each time an address A of the cell to be read; an XOR/ADDER block
4
, receiving from the matrix
3
the read data D and generating the signature Q; a master/slave unit
5
, storing the signature Q and having an output
6
for connection to the tester. A feedback control block
7
generates the feedback polynomial value FBP used by the XOR/ADDER block
4
to generate the signature Q according to the expression (1); to this end, the feedback control block
7
receives the signature Q. The signature Q is also fed to the XOR/ADDER block
4
. XOR/ADDER block
4
, master/slave unit
5
and feedback control block
7
form a signature generator
8
. The clock RD, fed from the tester, is also used for synchronizing the XOR/ADDER block
4
and the master/slave unit
5
.
The above described compression solution does not always ensure error detection; indeed, the possibility of obtaining the same signature from two different patterns is low but cannot be ruled out.
Later tests, carried out at Final Test Level or Final Device Characterization Level use high speed machines capable of detecting fault conditions not discovered at Wafer Sort Level. However, also the test machines used at final test level prove to be insufficient to truly satisfy the fast speed test requirements, so that complete memory test cannot be performed in production testing. Furthermore, any defective memories detected at those late stages cause higher costs for rejected devices.
The aim of the present invention is therefore to provide a test method with improved robustness against error masking.
SUMMARY OF THE INVENTION
According to the present invention, there are provided a test circuit and method and a nonvolatile memory device, having an internal clock that controls the memory array to read from a plurality of memory cells in a rapid fashion.
REFERENCES:
patent: 5761128 (1998-06-01), Watanabe
patent: 63 268199 (1988-11-01), None
patent: 407169300A (1995-07-01), None
patent: 407271628A (1995-10-01), None
patent: 409265799A (1997-10-01), None
patent: 02000011700A (2000-01-01), None
Carlson David V.
Galanthay Theodore E.
Nguyen Viet Q.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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