Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-24
2001-04-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000, C257S307000
Reexamination Certificate
active
06222217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device which restrains a leakage current in a n-p junction or a capacitor insulating film of a memory cell of a DRAM (Dynamic Random Access Memory), and to a manufacturing method thereof.
2. Description of the Background Art
Semiconductor memories are generally classified into three types: a DRAM (Dynamic Random Access Memory), a flash memory, and a SRAM (Static Random Access Memory). In the DRAM, data are refreshed and stored therein constantly, but when power is shut off thereto, the data once stored are lost. In the flash memory, data are perpetually stored therein and never lost even if power is shut off thereto. Therefore, the flash memory is referred to as a non-volatile memory. In the SRAM, data are not required to be refreshed, and when power thereto is shut off, the data once stored are lost. In this manner, each type of these semiconductor memories has its own characteristics, and is selected for use in conformity with their characteristics.
The DRAM is a leading memory occupying a greater production quantity of semiconductor memories at present. A DRAM includes a memory cell array serving as a storage region for storing a large quantity of storage information, and a peripheral circuit section for performing a predetermined input/output operation with respect to the memory cell array. The memory cell array further includes a plurality of memory cells arranged to perform as a minimum storage unit. Each memory cell basically includes a capacitor, and a MOS (Metal Oxide Semiconductor) transistor. In operation, whether or not a certain charge is stored in the capacitor is judged, and the judgment is associated with data of “0” and “1”, whereby the storage information is processed.
FIG. 34
shows an equivalent circuit of a memory cell of a background DRAM and in which reference numeral
201
designates a capacitor, and numeral
202
designates a cell transistor. The capacitor
201
and the cell transistor
202
form a memory cell
200
. Numeral
203
is a bit line, numeral
204
is a word line, and numeral
205
is a sense amplifier. As shown in
FIG. 34
, the capacitor
201
is connected to one of source/drain regions of the cell transistor
202
, and the bit line
203
is connected to the other of source/drain regions of the cell transistor
202
. Further, a gate electrode of the cell transistor
202
is connected to the word line
204
, and the bit line
203
is connected to the sense amplifier
205
.
The term “source/drain” is used herein because this element serves as a “source” to supply a carrier or as a “drain” to remove a carrier, depending on read or write of information.
FIG. 35
is a sectional view showing a construction of a background memory cell of which partially hidden parts are indicated by broken lines. In
FIG. 35
, reference numeral
101
is a semiconductor substrate, numeral
102
is an isolating oxide film forming a STI (Shallow Trench Isolation) in which one element is electrically insulated from other elements. Numeral
103
is a gate oxide film, and numeral
104
is a gate electrode forming the word line
204
. Numerals
105
and
106
are source/drain regions formed on left and right sides under the gate electrode
104
. Numeral
107
is a side wall which is an insulating film coating the gate electrode
104
. Numeral
1010
are polysilicon plugs, one of which is connected to the drain region
106
, and another of which is connected to a storage node contact
1017
later described. Numeral
1011
are polysilicon plugs, one of which is connected to the source region, and another of which is connected to the bit line
203
indicated by broken lines in FIG.
35
. Numerals
1012
and
1013
are silicon oxide films and numeral
1014
is a silicon nitride film.
These elements
1012
-
1014
form an interlayer insulating film. Numeral
1015
is a trench which is provided in such a manner to be open in the interlayer insulating film. Numeral
1017
is a storage node contact formed in the trench
1015
. Numeral
1019
is a storage node, numeral
1020
is a capacitor insulating film, and numeral
1021
is a cell plate. The capacitor insulating film
1020
is made of a nitride titanium film (TiN) and a tantalum oxide film (Ta
2
O
5
) formed on the surface thereof. The cell plate
1021
is composed of a polysilicon which includes n-type impurities. A capacitor
1022
is formed by the storage node
1019
, the capacitor insulating film
1020
and the cell plate
1021
.
A charge stored in the capacitor
201
as a storage information is gradually discharged due to a leakage current in the n-p junction between the source/drain regions
105
,
106
and the semiconductor substrate
101
or in the capacitor insulating film
1020
, etc. An operation of timely injecting a charge is required in order to maintain storage in the DRAM. This operation is called a “refresh”, in which information written in the capacitor
201
is judged by the sense amplifier
205
. That is, the read or write of information is performed so that a new charge is supplied when it is judged that a charge is injected in the capacitor
201
, and that the charge is exhausted in the capacitor
201
when it is judged that no charge is injected.
In addition, the refresh is performed by applying a voltage to the selected gate electrode
104
and the source/drain region
105
and by performing the read or write of the information stored in the capacitor
201
, as mentioned above.
In the background semiconductor device, however, information is lost due to generation of leakage current from the n-p junction of the storage node, the storage node contact and the source/drain region, in addition to the loss of information due to this read operation. In view of preventing the loss of information due to the leakage current, there has been a problem that the refresh must be performed on the information stored in every memory cell within a relatively short period of about 1 msec to several hundred msec. This refresh results in an increase in power consumption.
There has been another problem that, as the information stored in the memory cells cannot be read during the refresh, a refresh interval (refresh pause time) is shortened. If the refresh pause time is short, efficiency of data use per operating time is lowered.
There has been a further problem that minute defects are produced around the end of the isolating oxide film due to a stress caused by a difference in the coefficient of cubic expansion between the semiconductor substrate and the isolating oxide film, and a leakage current is generated due to such minute defects, which also shortens the refresh pause time.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-discussed problems and has as one object to provide a novel semiconductor device capable of restraining a leakage current of a n-p junction of a source/drain region and a manufacturing method thereof.
Another object of the present invention is to provide a novel semiconductor device capable of restraining a leakage current caused by minute defects produced due to stress around an end of an isolating oxide film and a manufacturing method thereof.
A further object of the present invention is to provide a novel semiconductor device capable of restraining a leakage current of a capacitor insulating film flowing through a storage node contact and a manufacturing method thereof.
A novel semiconductor device according to the present invention includes a semiconductor substrate. An isolating oxide film is formed on an isolated region of a main surface of the semiconductor substrate. A pair of source/drain regions is formed in an active region surrounded by the isolated region of the main surface of the semiconductor substrate. A trench is formed in the source/drain regions. A gate electrode is formed on the main surface of the active region of the semiconductor substrate through an insulatin
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thomas Tom
Tran Thien F.
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