Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1998-07-23
2001-03-13
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
06202165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject invention relates generally to synchronous digital systems and more particularly to an improved method and apparatus for clock generation in such systems.
2. Description of Related Art
A synchronous digital system is defined as having a single clock signal to which all activity in the system is synchronized. This signal is presently routed on metal wires throughout the system in much the same manner as every other signal in that system. Since the clock signal must go to every sequential element in the system, a very large and complex network results. The parasitics that this large network encounters cause delays in distribution of the clock signal, called clock skew. The maximum clock skew is subtracted from the clock period thus reducing the time budget for logic between sequential elements.
Typically, in the prior art, clock frequencies have been kept low enough that the skew component is small compared to total clock period. Another common practice is to over-constrain the combinatorial logic between sequential elements to be “safe” for any possible clock skew that may be produced for any particular routing of the clock network. Another approach which has been used is to employ phase lock loops to resynchronize clocks at various points a chip. Another approach that is seen in today's in desk top PC's is to run the processor chip at a higher frequency than the rest of the system, but phase locked to the lower system clock rate. One of the reasons for this approach is that high speed clock distribution over anything but the shortest distances (e.g. intrachip) is exceedingly difficult.
Early research was also done into distributing clocks by fiber optics, but such an approach has appeared impractical due to the complex problems presented by the necessity to mix materials in order to create a large and complex fiber network in a semi-conductor substrate or chip.
As system clock rates increase in synchronous digital systems and semiconductor fabrication geometries decrease, clock skew becomes a dominant factor in determining master clock frequency and thus maximum system performance. Concomitantly, the prior art approaches to dealing with clock skew become less and less acceptable.
SUMMARY OF THE INVENTION
The solution provided according to the invention is to apply light pulses to a substrate which causes simultaneous distribution of a system master clock throughout the substrate. Much as a strobe light in the middle of a room illuminates all objects throughout that room simultaneously, so the system clock generated photonically according to the invention triggers all sequential elements in the system simultaneously with essentially zero skew.
Apparatus according to the invention may comprise a light pulse generator disposed to expose a substrate to light pulses occurring at a system clock frequency, the light being of a wavelength selected to move photons simultaneously throughout the substrate. A plurality of photo responsive devices are distributed throughout the substrate causing a latching of data in response to the light pulses.
This technique thus permits a dramatic increase in system performance for synchronous digital systems. The larger the mechanical size of the system is the more benefit this approach provides because it offers essentially zero skew for even the largest assemblies. Implementation of the invention permits much higher system clock rates since the clock rate is roughly proportional to computational capability.
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Butler Dennis M.
Conexant Systems Inc.
Thomas Kayden Horstemeyer & Risley LLP
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