Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-16
2001-01-09
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S068000, C257S071000, C257S347000
Reexamination Certificate
active
06172388
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87117657, filed Oct. 26, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating high density integrated circuits, and more particularly to a method of fabricating dynamic random access memories (DRAM) with a thin film transistor (TFT) to increase the reading and writing speed.
2. Description of the Related Art
The higher the integration of memory devices is, the better the storage ability of a wafer is. In addition, the fabricating cost of a high integration memory device is cheaper than the fabricating cost of a low integration memory device. Therefore, the VLSI process usually provides as high a degree of integration as possible to increase the data storage ability of the wafer.
A conventional method of increasing the density of the memory devices of integrated circuits is to decrease part of the structure size of the memory devices of integrated circuits. This may be accomplished by a decrease in the size of the wiring lines, the size of the gate of the transistor or the size of the isolation region between memory devices. To decrease the size of the memory devices of integrated circuits means to decrease the design rules of the integrated circuits.
Generally speaking, a DRAM cell includes a transfer transistor (or a field effect transistor) and a capacitor. Conventional method of storing the DRAM data is by selectively charging or discharging each of the capacitors formed on the semiconductor substrate to store the DRAM data. That is, a two-bit data can be stored in a capacitor by using the discharging state indicated by logic “0” or the charging state indicated by logic “1”. The steps of the method of storing the DRAM data includes providing electrical voltage to the gate of the transistor to store charges in the capacitor. The amount of charge stored in the capacitor depends upon the surface of the capacitor electrode, the dielectric coefficient of the dielectric layer of the capacitor and the distance between the upper electrode and the lower electrode (e.g. the thickness of the dielectric layer). The reading operation of the DRAM is performed by using the field effect transistor (FET) to selectively couple the storage capacitor to the bit line, and to transfer charges to the capacitor or retrieve charges from the capacitor. The contact formed between the bit line and the FET is one of the source/drain electrodes of the FET, and another source/drain electrode of the FET is connected to the capacitor. Accordingly, the bit line is connected to the lower electrode of the capacitor via the FET. The signal of the word line is provided from the gate of the FET to transfer the charges between the bit line and the storage capacitor.
As the size of the DRAM minimizes according to the design rule, the surface of the lower electrode of the capacitor decreases. The conventional capacitor is planar in structure. The shrinkage of the surface of the lower electrode of the capacitor thus decreases the amount of the storage charges (e.g. the capacitance). The decreasing of the amount of the storage charges will result in some problems, such as decay mechanisms and charge leakage that result in data loss. Therefore, the capacitor must frequently receive supplementary charge to maintain the amount of the storage charges in the capacitor to resolve the problem of the charge leakage or data loss. The supplementary charges to the capacitor are called refresh cycles. During refresh cycles, the DRAM cannot store or read data. If the charge storage performance decreases, it is necessary to provide a more complicated refresh cycle operation or a more sensitive charge sensor amplifier. Therefore, as the size of the DRAM minimizes according to the design rule, it is necessary that the surface of the lower electrode of the capacitor increase to overcome the problem of charge leakage or data loss.
FIGS.
1
A-
1
C are schematic, cross-sectional views showing a conventional process of fabricating a DRAM. As shown in
FIG. 1A
, a shallow trench isolation (STI) structure
102
is formed on a substrate
100
. A gate oxide layer
104
and a gate electrode
106
are formed on the substrate
100
. A source/drain region
108
is formed in the substrate
100
and beside the gate electrode
106
. An isolating layer
110
, for example, an oxide layer, is formed on the gate electrode
106
and the substrate
100
. The isolating layer
110
is patterned to form a contact opening
112
.
As shown in
FIG. 1B
, a conductive layer
114
is formed on the isolating layer
110
and in the contact opening
112
to form a contact
112
a
that electrically connects one of the source/drain regions
108
.
As shown in
FIG. 1C
, the conductive layer
114
is patterned to form a conductive layer
114
a
. A hemispherical grain (HSG) layer
115
is formed on the conductive layer
114
a
. Accordingly, the contact
112
a
, the conductive layer
114
a
and the HSG layer
115
together form a lower electrode of a capacitor. A dielectric layer
116
is formed on the HSG layer
115
. A conductive layer
118
is formed on the dielectric layer
116
to form an upper electrode of the capacitor.
As the size of the DRAM is minimized according to the design rule, the surface of the lower electrode of the capacitor decreases. The sensitive range of the DRAM and the speed of reading or writing are all poor. It is necessary to provide a method to improve the sensitive range of the DRAM and the speed of reading or writing.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of fabricating DRAM with a thin film transistor (TFT) to increase the reading and writing speed.
It is another object of the invention to provide a method of fabricating a DRAM with a thin film transistor (TFT). If the voltage of the charge storage is higher than the threshold voltage of the thin film transistor (TFT), the data of charging state “1” can be read correctly. Because the thin film transistor (TFT) can provide enough charges to the circuit, the sensitive range of the DRAM improves and the speed of reading and writing improves.
A method of the process according to the invention comprises the following steps. A substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line. The terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact and to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region. The drain region is on one side of the terminal contact corresponding to the source region.
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patent: 4716548 (1987-12-01), Mochizuki
patent: 4746959 (1988-05-01), Mueller
patent: 4751557 (1988-06-01), Sunami et al.
patent: 5219779 (1993-06-01), Suzuki
patent: 5270968 (1993-12-01), Kim et al.
patent: 5447879 (1995-09-01), Park
patent: 5585284 (1996-12-01), Park
patent: 5821564 (1998-10-01), Wu et al.
Carroll J.
Huang Jiawei
J.C. Patents
United Semiconductor Corp.
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