Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
1999-06-15
2001-03-13
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S711000, C714S718000, C365S201000
Reexamination Certificate
active
06202179
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to memory devices, and more particularly to such memory devices having a data compression test mode.
BACKGROUND OF THE INVENTION
Semiconductor memories such as dynamic random access memories have literally millions of memory storage cells. These storage cells are typically fabricated having individual capacitors as the memory elements and include access transistors. The cells are arranged in rows and columns. A memory cell array refers to these cells as they are organized in rows and columns. To ensure that a particular memory device is fully operational, each of the individual memory cells within the device is operationally tested.
As semiconductor memory technology has evolved, the typical memory device has increasingly stored more and more individual memory cells. This increase in the population of memory cells in a memory device has correspondingly increased the possibility of defects within one or more memory cells and has also increased the time required to test all the cells. Therefore, the need for rapidly testing the cells of a memory device has become even more crucial.
However, because the typical memory device has so many individual memory cells, testing each individual cell can be quite time consuming. A typical testing method writes a test bit to a memory cell, reads an output bit from the memory cell, and compares whether the output bit is identical to the test bit. This last step is the error-checking step. If an error is found—i.e., the output bit is not identical to the test bit—then a redundant memory cell is used to replace the defective cell.
Because this testing method is so time consuming, various solutions have been proposed to decrease testing time. One typical solution is to write a test bit to a predetermined number of memory cells concurrently, reading the output bits of the memory cells, compressing the output bits into a compressed bit, and error checking just the compressed bit. If at least one of the predetermined number of memory cells is defective, the compressed bit will be in error.
This solution is typically called data compression test mode. It is less time consuming in that a number of memory cells are tested at one time, as opposed to each memory cell being tested one at a time. A deficiency to data compression test mode, however, is its inefficient redundancy. If error checking the compressed bit fails, then all of the predetermined number of memory cells are replaced with redundant cells. Thus, if the predetermined number of cells is seven, even if only one of the seven cells is defective, all seven cells are replaced by redundant cells. In other words, the fault-isolation capability of the data compression test mode is severely reduced.
Therefore, for the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification as disclosed herein, there is a need for a data compression test mode that provides more efficient redundancy. That is, there is a need for a data compression test mode that replaces only those memory cells that are defective, instead of all of the predetermined numbered of memory cells tested, and thus which provides for a more accurate fault-isolation technique.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention, which will be understood by reading and studying the following specification. The present invention relates to a data compression test mode, independent of redundancy, for a memory device. A memory device is described which has a data compression test mode that tests at one time a predetermined number of memory cells for defects, but in which only those cells that actually are defective are replaced.
In particular, in one embodiment of the invention, a method for testing a memory array of a memory device includes outputting the output bits of a predetermined number of memory cells, upon failure of the compression mode. The cells may then be checked for errors and replaced if necessary on an individual basis. In this manner, the present invention provides for a data compression test mode independent of redundancy. The memory cells of a memory array are still checked for defects a predetermined number at a time in a compression mode. However, upon the detection of an error within the compression mode, the cells are individually checked for errors to determine which of the cells are actually defective. Only these cells are replaced.
In another embodiment, a memory device includes an array of memory cells, and a compression test mode circuit such that only the cells that are defective are replaced with redundant cells. That is, the circuit checks a number of memory cells at one time in a compression mode, but outputs individually the output bits of the cells upon failure of the compression mode. Still other and further aspects, advantages and embodiments of the present invention will become apparent in the following description and by reference to the accompanying drawings.
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Micro)n Technology, Inc.
Moise Emmanuel L.
Schwegman Lundberg Woessner & Kluth P.A.
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