Static information storage and retrieval – Read/write circuit – Noise suppression
Reexamination Certificate
2000-04-14
2001-07-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Noise suppression
C365S226000
Reexamination Certificate
active
06266288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits, and, more particularly, to reducing the effects of power supply distribution related noise in integrated circuits.
2. Description of the Related Art
The demand for faster and more powerful personal computers has led to many technological advances in the computer industry, including the development of faster microprocessors and very large scale integration (VLSI) chips. The new generation of microprocessors and VLSI chips generally tend to consume more power than the previous generation.
To reduce the power consumption, logic designers have entertained several options, including reducing the supply voltage V
cc
. The general trend has been to reduce the supply voltage V
cc
by approximately 30 percent per generation, which has resulted in power savings of approximately 50 percent. However, because the effective switching capacitance and the frequency of operation of the VLSI chip are increasing at a high rate from one generation to another, the net effect has been an increase in the power consumption in the VLSI chip.
While reducing the supply voltage V
cc
results in power savings, such supply voltage scaling can be done only to a limited extent. This is because the supply voltage scaling does not reduce the supply currents by the same proportion as the power consumption. That is, while the power consumption is reduced quadratically, the supply current is reduced only linearly. As a result, the parasitic effects of resistances and inductances, in the circuit worsen, thereby increasing the power supply distribution related noise. The power supply distribution related noise is caused by the voltage drops across the resistors and the inductors. Furthermore, the supply voltage scaling reduces the noise margin of the circuits on the VLSI chip, which makes the circuits more susceptible to the power supply distribution related noise.
One method offered by the prior art to reduce the effects of power supply distribution related noise is illustrated in FIG.
1
. As shown in
FIG. 1
, the load circuit
5
is coupled to a power supply grid
10
that is inherently inductive and resistive. Whenever the inductance and the resistance of the power supply grid
10
momentarily impedes the current supplied to the load circuit
5
, a decoupling capacitor
15
provides the necessary charge to the load circuit
5
. Thus, the decoupling capacitor
15
restores the voltage level required for the proper operation of the load circuit
5
. It should be noted that the size of the decoupling capacitor
15
has to be large enough to provide adequate charge (i.e. current) until the power supply to the load circuit
5
is restored.
Generally in VLSI chips, metal-oxide-semiconductor field-effect transistors (MOSFETs) (not shown) are employed as the decoupling capacitors
15
in the logic technology. The MOSFETs consume little space and are able to provide a high amount of capacitance that is capable of storing enough charge to drive the load circuit during the periods the voltage level drops. Specifically, MOSFETs have a thin gate oxide and an insulating material with a relatively high dielectric constant. Thus, at least for today's logic chips, the MOSFETs are capable of serving as adequate decoupling capacitors
15
.
While the prior art method of utilizing MOSFETs as decoupling capacitors
15
is adequate for reducing the effects of the power supply distribution related noise, it still suffers from at least one shortcoming. As the future generation of more powerful and faster processors and VLSI chips emerge, a higher amount of capacitance will be necessary to reduce the effects of the power supply distribution related noise. This means that larger-size MOSFETs will be required to serve as decoupling capacitors
15
to achieve the increased demand for capacitance. But larger-size MOSFETs will increase the size of the chips, thereby making the prior art method less cost effective. Thus, what is needed is an effective method of reducing the effects of the power supply distribution related noise that demands very little estate on a chip.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for reducing the effects of power supply distribution related noise in an integrated circuit, the integrated circuit having a power supply bus, a ground bus, a DRAM-technology capacitor, and a load circuit. The method includes forming the DRAM-technology capacitor adjacent the load circuit, and connecting the DRAM-technology capacitor directly between the supply voltage bus and the ground voltage bus.
A method is provided for reducing the effects of power supply distribution related noise in an integrated circuit, the integrated circuit having a power supply bus, a ground bus, a DRAM-technology capacitor, and a non-memory load circuit. The method includes forming the DRAM-technology capacitor adjacent the non-memory load circuit, and connecting the DRAM-technology capacitor directly between the supply voltage bus and the ground voltage bus.
REFERENCES:
patent: 5455192 (1995-10-01), Jeon
patent: 5801412 (1998-09-01), Tobita
patent: 5838038 (1998-11-01), Takashima et al.
patent: 6111804 (2000-08-01), Borkar
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nelms David
Tran N.
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