Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
1998-11-12
2001-05-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S482000
Reexamination Certificate
active
06235613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to the field of semiconductor integrated circuit fabrication and, in particular, to the field of fabrication of capacitors within semiconductor integrated circuits.
2. Background Art
The miniaturization of electrical components and their integration on a single piece of semiconductor material has been the catalyst for a worldwide information revolution. As integrated circuit technology has progressed, it has become possible to store and process increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly and reliably. One of the most important areas where this miniaturization has occurred has been in the area of dynamic random access memory (DRAM). Miniaturization has also occurred in many other areas of semiconductor fabrication.
As this trend continues, one of the integrated circuit structures which must be miniaturized is capacitors. For example, DRAMs are formed of a large number of storage nodes which require transistors and capacitors in order to store information.. The state of the art of fabricating the storage nodes of DRAM circuits has progressed to the point where the transistors of the DRAM nodes can be made much smaller than the capacitors. Thus the shrinking of capacitors is an important goal in the continuing trend of miniaturizing DRAM circuits.
In order to reach this goal, the smaller capacitors must possess a minimum amount of capacitance and permit the sense amp to accurately determine the contents of the node. If a capacitor has too little capacitance it loses the charge placed upon it too quickly, causing it to have errors in data storage. Thus, it is essential that the electrodes of storage node capacitors be large enough to accurately store an adequate charge in spite of parasitic capacitances and noise that may be present during circuit operation.
The capacitance, C, of a capacitor depends upon the dielectric constant, &egr;, of the material placed between the electrodes of the capacitor, the distance, d, between the electrodes, and the effective surface area, A, of the electrodes. The relationship may be expressed C=A&egr;/d. In many cases the material used as the dielectric between the electrodes of the capacitor is limited to only a few possibilities. Also, the minimum distance between the capacitor electrodes is generally limited to a particular value in order for~the number of fabrication defects to be kept to an acceptably low value. For example, the minimum distance between the plates of the capacitor is determined by the breakdown field of the dielectric material. For a given voltage, if the capacitor plates are too close together, the electric field in the dielectric material exceeds its breakdown value and the dielectric fails. Thus, the parameter that can most easily be varied to obtain increased storage capacity in DRAM capacitors is the effective surface area of the capacitor electrodes.
Therefore, it is a goal of capacitor miniaturization to maximize the effective surface area of capacitor electrodes as much as possible. Various three dimensional structures have been proposed and adopted in order to maintain the value of capacitors at a high level while keeping the planar surface area of the DRAM, or the footprint area, allocated to the capacitor at a minimum. Among the proposed methods for maintaining cell capacitance while decreasing the footprint area devoted to the cell capacitor is one described in Lu, N. C. C., “Advanced Structures for Dynamic RAMs”, IEEE
Circuits and Devices Magazine
, pages 27-35, (January, 1989).
Lu describes a trench transistor cell in this reference. In the trench transistor cell described in the Lu paper, the capacitor cell is a vertical structure with an access transistor which is also vertical. The access transistor is placed above the cell capacitor. The described trench cell provides greater capacitor electrode area in a small footprint area when compared to many planar capacitor structures. However, methods of this type do not address the problem of increasing the effective surface area of the-electrodes of capacitors.
It is well known in the prior art of semiconductor fabrication that the storage capacitance of a capacitor can be enhanced without increasing either the footprint area or the storage electrode height by using hemispherical grain silicon (HSG) to form a capacitor electrode. The increase in capacitance provided by the use of HSG is due to the increase in the surface area of the electrodes. The increase in the surface area of the electrodes is due to the presence of the grains and the shape of the grains on the surface of the polysilicon forming the electrodes.
Many methods for forming HSG are known in the prior art. The known methods include low- pressure chemical vapor deposition (CVD), cold wall CVD, and seeding a layer of amorphous silicon followed by annealing of the layer. In the seeding and annealing method a layer of amorphous silicon is seeded, for example with silane or disilane, in order to form crystals upon the surface of the amorphous silicon material. The amorphous silicon material is then annealed to form the grains of the HSG around the seeds. The annealing of the seeded amorphous silicon can be performed at a temperature in excess of approximately 450° C. In this process, nucleation begins on the surface of the silicon as the gas is bled into the reaction chamber and the silicon is exposed to the heat and vacuum anneal. In this manner the smooth silicon is transformed into rugged HSG silicon.
In the low pressure CVD method for forming HSG, silicon is deposited while the temperature is in the transition regime from amorphous silicon to polycrystalline silicon. This is performed at about 555° C. at a pressure of 190 mtorr. Silane is typically used as a precursor for this deposition. If the deposition takes place at a lower temperature amorphous silicon is deposited. If the deposition takes place at a higher temperature, polycrystalline silicon is deposited. In the transition regime HSG is deposited.
In a typical example of the known methods for forming HSG, as shown in
FIG. 1
, HSG layer
18
is formed within an electrode structure
10
over a doped silicon layer
12
in a processing reactor such as a conventional CVD chamber. Doped silicon layer
12
could, for example, be doped polysilicon or a doped amorphous silicon layer. When the doped polysilicon layer
12
is formed a flow of dopant is provided while the polysilicon material is deposited. The depositing of polysilicon layer
12
could be performed, for example, at approximately 625° C. and 150 mtorr.
However, using the low pressure CVD method, the depositing of HSG layer
18
could not be performed directly upon the surface of the doped silicon layer
12
. Therefore, after formation of the polysilicon layer
12
, a thin layer
14
of native oxide is formed upon the surface of polysilicon layer
12
, by a reaction with oxygen in the air as the wafers were pushed into the deposition furnace after a hydrofluoric acid clean to prepare the surface. Typically, native oxide layer
14
is formed with a thickness of approximately ten angstroms. Native oxide layer
14
formed in this manner provided a disordered surface upon which the HSG layer
18
could be formed.
However, native oxide layer
14
somewhat degraded the electrical properties of the integrated circuit. Furthermore, in order to form native oxide layer
14
using this prior art method, electrode structure
10
had to be removed from the furnace for cleaning. This added expense to the process of fabricating electrode structure
10
.
Another prior art method for forming the native oxide layer
14
of electrode structure
10
, the O
2
flash method, permitted the formation of native oxide layer
14
in situ. Forming the oxide layer
14
in situ-in the O
2
method eliminated the additional expense of removing electrode structure
10
from the polysilicon furnace of the CVD chamber to perform the oxidation step. However, performing the O
Micro)n Technology, Inc.
Nelms David
Nhu David
Reed Smith LLP
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