Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
1999-06-18
2001-03-06
Whitehead, Jr., Carl (Department: 2872)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C600S553000, C600S553000, C600S593000
Reexamination Certificate
active
06197621
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated-circuit technology and, more particularly, to a method for post-manufacturing custom-modification of an integrated circuit. A major objective of the present invention is to provide a simple, economical, and reliable method of linking metal conductors of an integrated circuit.
Advances in integrated-circuit manufacturing technology have allowed ever increasing functionality to be implemented on a single device. A typical integrated circuit includes: a silicon substrate with regions doped to control their conductivity type, field and gate oxides for electrically isolating the substrate from overlaying conductors, one or more polysilicon layers for forming contacts and local interconnects, a submetal dielectric layer, a metal interconnect structure, and a passivation layer.
The metal interconnect structure can have one or more metal layers. Where there are plural metal layers, the layers are separated by intermetal dielectric, usually at least as thick as the underlying metal. In addition, the submetal and intermetal dielectrics are often planarized so that the next metal layer can be formed on a flat surface. The passivation layer tends to be thinner, since it is not required to isolate conductors, and not planarized, since it is not used as a base for subsequently formed features.
As integrated circuit designs have become more complex, it has become increasingly difficult to ensure that a design properly implements all its intended functions. Accordingly, prototypes must be built and tested before a commitment is made to a large volume run. However, small-volume prototype runs can be quite expensive and time consuming. If a design defect is found in a prototype, it is desirable to verify the new design prior to starting over to make a new prototype.
One increasingly popular prototyping approach uses electrically (e.g., “field”, or “user”) programmable devices. The functions performed by such devices are determined after manufacture by electrically programming the device. If defects in the programming of a first device are discovered, a second device can be correctly programmed and substituted for the first device. Even more convenient are electrically reprogrammable devices in which a defective design program can simply be overwritten by a corrected program. However, the variations that can be implemented by programming are limited by the circuit as designed into the programmable device. If the circuitry of the programmable device is defectively designed, the defect cannot in general be corrected by reprogramming the device or by substituting a nominally identical device with different programming. Thus, even with programmable and reprogrammable devices, the problem of correcting defectively designed hard circuitry remains.
In an “antifuse” approach to electrically programming a circuit, a large voltage differential is applied across two adjacent conductors (on the same or different layers) so that the intervening dielectric breaks down, thus creating a link. A problem with the antifuse approach is that the resulting link has relatively high impedance, so large currents, e.g., driver currents, cannot be handled. Furthermore, the antifuse approach is limited to creating links, whereas it is desirable to be able to create reliable opens along existing conductors as well.
It is also possible to physically modify an integrated circuit to create an open. For example, a laser can be used to cut a conductor to create an open. However, the laser energy disrupts the overlaying dielectric, impairing the predictability of the modification as well as the long-term reliability performance of the circuit.
Focused ion beam systems have been used to make connections as well as break them. A focused, rasterized beam of high-energy ions, e.g., gallium ions, can be used to sputter and remove dielectric over metal lines. If a break is desired, the beam can be used to precisely cut through the metal. If a new connection is desired between thus exposed conductors, the metal itself is left undisturbed; metal-bearing, e.g., tungsten carbonyl, gas is admitted into the vacuum chamber. The ion beam is scanned from one metal electrical node to the other. The ion beam locally decomposes the metal-bearing gas adsorbed onto the surface, leaving a conductive trace between the metal electrical nodes. This technique is very flexible, permitting connections even between nodes that are on the same or different metal interconnect levels and disposed far apart on the integrated circuit.
The main advantage of the focused ion beam approach is that it allows flexible modification of an integrated circuit, both before and after integrated circuit manufacture is completed. The focused ion beam approach is costly in that the equipment is expensive and requires a high degree of skill on the part of the operator. If circuit breaks are required in isolated lines, the laser cutting approach is most cost effective. However, as with laser cutting, the focused ion beam damages intermetal and passivation dielectric, the effects of which can be difficult to predict and control. Accordingly, devices so modified are best limited to design verification purposes; newly designed and manufactured devices are still required for end uses.
What is needed is an improved method of modifying integrated circuits. It should provide for making connections as well as breaking them. Yet, the method should be more economical and less destructive than the focused ion be a m method.
SUMMARY OF THE INVENTION
In accordance with the present invention, a laser beam is directed through an intact dielectric to link two metal conductors of an integrated circuit. The minimum dielectric thickness above the conductors is greater than, and is preferably at least twice, the maximum thickness of the conductors in order to maintain mechanical integrity during the procedure. The conductors are preferably spaced a distance less than twice their maximum thickness.
The wavelength of the laser is selected so that it is absorbed much better by the metal than by the dielectric material. For dielectrics and metals commonly used in integrated circuits, visible light lasers of sufficient power tend to be suitable. In practice, the method involves placing the integrated circuit (which may still be on a wafer or already mounted in a package) under a microscope. Using a target light to illuminate an area covering the two metal features to be linked and then pulsing the laser. The selected laser power is sufficient to fuse the metals so that they flow into contact, but insufficient to delaminate or ablate the overlaying dielectric.
The thickness of the overlaying dielectric is selected to provide the strength required to resist stress caused by the laser and subsequent deformation of the underlying metal. The required thickness is conventional achieved i n integrated circuits with multi-layer metal interconnect structures, as long as the conductors to be linked are on a metal layer other than the top metal layer. Accordingly, the method can be applied to many integrated circuits designed without the present invention in mind. However, a much greater range of electrical modifications can be provided for if the integrated circuit is designed with consideration given to subsequent laser linking of conductors.
Accordingly, an integrated circuit can be manufactured so that the passivation layer over the top metal layer has a minimum thickness at least as great, and preferably at least twice as great, as the metal conductor thickness. In addition, the passivation layer can be planarized to optimize its optical transmission characteristics and improve the efficiency of laser energy delivery to the conductors. In this case, the passivation layer can be similar to conventional intermetal dielectric layers. However, the purpose of the structure is different since the thickness is not required for electrical insulation or for forming structures thereon. The invention thus provides for the pre-linking integrated circ
Anderson Clifton L.
Guerrero Maria
Jr. Carl Whitehead
VLSI Technology Inc.
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