Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-10-01
2001-04-17
Whitehead, Jr., Carl W. (Department: 2503)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S384000
Reexamination Certificate
active
06218710
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a process in which Metal Oxide Silicon Field Effect Transistors (MOSFET), devices are fabricated using specific semiconductor fabrication techniques to improve yield and performance.
(2) Description of Prior Art
Very large scale integration (VLSI) technologies have helped the electronic chip industry reduce cost while still increasing chip and circuit performance. Further improvements in cost and performance strongly depends on the ability of the semiconductor process community to either continue to decrease chip size or use less resistive films.
The advances in lithograhy, such as more advanced cameras, or more sensitive photoresist materials, have allowed important features of semiconductor chips to decrease in size thus improving density as well as performance. The reduction ingate electrode dimensions have resulted in narrower channel lengths of FET devices, thus improving performance. However the narrower polysilicon gates are less condutive than their wider counterparts, thus a decrease in performance can result. One method to overcome the resistive aspect of narrower polysilicon gates is via the use of silicided polysilicon gates.
There are several methods for preparing silicided polysilicon gates. One can deposit, either via chemical vapor deposition, (CVD), or vacuum processes, a silicide such as titaniumn silicide, (TiSi2), on a blanket ploysilicon layer and use standard lithography and RIE processes to define a silicide/polysilicon gate. U.S. Pat. No. 5,089,432, by Yoo, shows this process. The use of this technique does not allow the source and drain regions to benefit from this process, since these regions are defined after the polysilicon gates have been formed. A method that does allow both the polysilicon gate as well as the source and drains to be silicided is a self-aligned process, usually referred to as salicide.
The salicide process is accomplished by depositing a metal, such as titanium, (Ti), on the patterned gate and source-drain. The polysilicon gate had previously been subjected to an insulator/reactive ion etching, (RIE), process to create a insulator sidewall which is needed for this salicide process. When these structure are subjected to an anneal step, TiSi2 will form only on the exposed silicon regions, such as the top of the polysilicon gate and the source-drain areas. Ti will remain unreacted on non silicon regions, such as the the polysilicon insulator sidewall. A selective etch is than used to remove the unreacted Ti, not significantly attacking the TiSi2, and thus arriving at low resistance silicided gates and source-drains, isolated by the polysilicon insulator sidewall.
One yield detractor associated with the self aligned process is bridging between the polysilicon gate and the source-drain. This arises from either Ti not being removed by the selective etchant, or somehow the anneal process created TiSi2 on the sidewall and thus the etchant was ineffective. Thus the semiconductor industry is still investigating process sequences that would reduce or eliminate the bridging phenomena.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a shallow junction FET device in which the source and drain of this device is formed by diffusion from an overlying doped polysilicon layer.
It is another object of this invention to self align the poly silicon gate to an already fabricated source and drain region.
It is still another object of this invention to created a polysilicon gate shape, wider at the top than the bottom, that will subsequently result in shadowing of metal depositions.
And still a further object of this invention is to form a self aligned silicide, on the polysilicon gate as well as the source and drains, with reduced risk of gate/substrate shorts due to bridging.
In accordance with this present invention, a method is described for fabricating a MOSFET device by forming a field oxide pattern and an anti-punch thru region on a silicon substrate. Depositing a polysilicon layer on the field oxide and the exposed silicon substrate and than depositing a silicon nitride layer over the polysilicon layer. Openings thru the silicon nitride and polysilicon layers are made to the substrate and a threshold adjust ion implant, (I/I), is performed. A spacer oxide is than fabricated on the sidewall of the opening followed by a gate oxidation of the exposed silicon substrate in the opening. A second polysilicon layer is deposited over the silicon nitride layer and the gate oxide. The second polysilicon layer is patterned to overlap the opening in the silicon nitride-first polysilicon layers and thus after complete removal of the silicon nitride layer, the second polysilicon overhangs the first polysilicon layer. Ion implantation is performed to dope the polysilicon gate electrode, (second polysilicon), as well as the the first polysilicon layer which after an anneal result in formation of the source-drain regions in the substrate. Titanium is than deposited on all regions except under the the overhang. After an anneal to form the metal silicide on the regions where Ti interfaced silicon, not insulator, removal of the unreacted Ti is performed in a selective etchant. After an additional anneal to reduce the resistivity of the silicide an insulator is deposited and holes opened to the polysilicon gate and the source-drain regions. Metallization and subsequent patterning is performed to contact the gate polysilicon and the source-drain regions.
REFERENCES:
patent: 5089432 (1992-02-01), Yoo
patent: 5270240 (1993-12-01), Lee
patent: 5270256 (1993-12-01), Bost et al.
patent: 5381028 (1995-01-01), Iwasa
patent: 5411906 (1995-05-01), Johnson et al.
Ackerman Stephen B.
Industrial Technology Research Institute
Saile George O.
Whitehead Jr. Carl W.
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